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    2.
    发明专利
    未知

    公开(公告)号：FR2411442B1

    公开(公告)日：1986-01-31

    申请号：FR7830983

    申请日：1978-10-24

    Applicant: IBM

    Inventor： BEISMANN WALTER F ,  LAMPE HANS H ,  POHLE WERNER H

    IPC: G06F9/48 ,  G06F9/18

    Abstract: In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests-e.g., supervisor programs-a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs.

    ARRANGEMENT FOR PROGRAM INTERRUPTION
    4.
    发明专利
    ARRANGEMENT FOR PROGRAM INTERRUPTION 未知

    公开(公告)号：AU4192478A

    公开(公告)日：1979-06-14

    申请号：AU4192478

    申请日：1978-11-24

    Applicant: IBM

    Inventor： BEISMANN WALTER F ,  LAMPE HANS H ,  POHLE WERNER H

    IPC: G06F9/48 ,  G06F9/18

    Abstract: In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests-e.g., supervisor programs-a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs.

    ARRANGEMENT FOR THE DYNAMIC DIRECT DIGITAL DISPLAY OF PULSE RELATIONS
    5.
    发明专利
    ARRANGEMENT FOR THE DYNAMIC DIRECT DIGITAL DISPLAY OF PULSE RELATIONS 未知

    公开(公告)号：CA1019482A

    公开(公告)日：1977-10-18

    申请号：CA213087

    申请日：1974-11-05

    Applicant: IBM

    Inventor： LAMPE HANS H ,  RUDOLPH PETER ,  HAHN GUENTER

    IPC: G01R13/00 ,  G01R13/40

    Abstract: An arrangement for the dynamic direct display of pulses in the nanosecond range operates without oscilloscopes or other special display apparatus. To display pulse timing or amplitude characteristics, a pulse sequence is applied to an equidistant tapped delay line, the output from each tap being connected to a bistable storage element with an indicator lamp in the output. A plurality of indicator lamps are arranged in the form of a matrix. If a pulse occurs on a tap during a sampling interval, the associated indicator lamp is turned on. The sequence and identity of the turned on indicators is indicative of the pulse spacing and the pulse width in the pulse sequence.

    ARRANGEMENT FOR PROGRAM INTERRUPTION
    7.
    发明专利
    ARRANGEMENT FOR PROGRAM INTERRUPTION 未知

    公开(公告)号：CA1115851A

    公开(公告)日：1982-01-05

    申请号：CA317422

    申请日：1978-12-05

    Applicant: IBM

    Inventor： BEISMANN WALTER F ,  LAMPE HANS H ,  POHLE WERNER H

    IPC: G06F9/48 ,  G06F9/00

    Abstract: ARRANGEMENT FOR PROGRAM INTERRUPTION In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests -- e.g., supervisor programs -- a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs. GE9-76-023

    METHODS OF IMPROVING THE MEASURE AND DISPLAY PRECISION IN AN ARRANGEMENT FOR INTERROGATING AND REPRESENTING RAL VALUES TO BE MEASURED
    8.
    发明专利
    METHODS OF IMPROVING THE MEASURE AND DISPLAY PRECISION IN AN ARRANGEMENT FOR INTERROGATING AND REPRESENTING RAL VALUES TO BE MEASURED 未知

    公开(公告)号：CA1049152A

    公开(公告)日：1979-02-20

    申请号：CA228405

    申请日：1975-06-03

    Applicant: IBM

    Inventor： LAMPE HANS H ,  RUDOLPH PETER ,  DEUERLEIN ARTHUR

    IPC: G01D7/00 ,  G01R13/28 ,  G06F11/32 ,  G06F13/00 ,  G06F17/40 ,  H03K13/02

    Abstract: Methods Of Improving The Measure And Display Precision In An Arrangement For Interrogating And Representing Several Values To Be Measured This invention provides a method of improving the measure and display precision in an arrangement for interrogatinq several values to be measured which are picked up by input/output devices or service processors of a computer system, and generally by discrete and discretely addressable functional units, where the individual functional units are connected to an address channel and predetermined addresses are associated thereto, and where furthermore the individual functional units are connected to a measure data channel via which, after addressing and switchinq, data are transferrable to a central location, and where for the time representation of these measure values on a display device, all desired measure positions of the one service processor selected by means of the selected address being switched simultaneously via the central measure data channel with a central measuring processor, a trigger signal supplied by the selected service processor and applied on a measure data channel line is selectable for synchronization, this trigger signal furthermore causing the central measuring processor to start interrogating in predetermined intervals all measure data signals on the measure data channel simultaneously, and where finally the momentary measure values in that interrogation are stored in a storage and displayed in parallel and simultaneously in different lines on the alphanumeric screen used as display device with column and line representation, the screen having a storage where all characters displayed on the screen can be stored and used again and again for display, and where each column of the screen has an associated interrogation pulse, characterized in that upon each second newly triggered cycle the interrogation pulses, relative to the interrogation pulses of the preceding cycle, are staggered as a whole with respect to time, said time staggering being relatively small regarding the spacing of two interrogation pulses.

    ARRANGEMENT FOR DETERMINING THE LENGTH OF ARBITRARY SHIFT REGISTERS
    9.
    发明专利
    ARRANGEMENT FOR DETERMINING THE LENGTH OF ARBITRARY SHIFT REGISTERS 未知

    公开(公告)号：CA1125913A

    公开(公告)日：1982-06-15

    申请号：CA333248

    申请日：1979-08-07

    Applicant: IBM

    Inventor： DRESCHER HEINZ ,  IMBUSCH HEINRICH ,  LAMPE HANS H

    IPC: G01R31/3185 ,  G06F11/22 ,  G11C19/00 ,  G11C29/00 ,  G11C19/28

    Abstract: An arrangement for determining the length Lx of arbitrary shift registers, which registers may be in the form of test objects, not exceeding a predetermined maximum length Lmax, wherein the arrangement is connected to an input of the test object for generating a test shift pattern of length Lmax + K, with K?2 which consists of a defined bit configuration. that is only binary ones, with a defined data transition at its end facing the test object and which is shifted through the test object, a storage of the length Lmax + K which is connected to an output of the test object and which, a the shift pattern is shifted, accommodates the information of the length Lx of the test object and the part Lmax + K - Lx of the test shift pattern and a display field, whose individual fields are permanently associated with one storage cell, each of the storages indicating the content of the cell, so that the data transition, and thus the end and the length Lx, of the test object can be determined.

    10.
    发明专利
    未知

    公开(公告)号：FR2411442A1

    公开(公告)日：1979-07-06

    申请号：FR7830983

    申请日：1978-10-24

    Applicant: IBM

    Inventor： BEISMANN WALTER F ,  LAMPE HANS H ,  POHLE WERNER H

    IPC: G06F9/48 ,  G06F9/18

    Abstract: In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests-e.g., supervisor programs-a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs.

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