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    RAM BASED IMPLEMENTATION FOR SCALABLE, RELIABLE HIGH SPEED EVENT COUNTERS
    1.
    发明申请
    RAM BASED IMPLEMENTATION FOR SCALABLE, RELIABLE HIGH SPEED EVENT COUNTERS 审中-公开
    基于RAM的可扩展，可靠的高速事件计数器的实现

    公开(公告)号：WO2010012633A3

    公开(公告)日：2010-06-24

    申请号：PCT/EP2009059395

    申请日：2009-07-22

    Applicant: IBM ,  IBM UK ,  BENDER CARL ALFRED ,  HOCHSCHILD PETER HEINER ,  MISRA ASHUTOSH ,  SWETZ RICHARD

    Inventor： BENDER CARL ALFRED ,  HOCHSCHILD PETER HEINER ,  MISRA ASHUTOSH ,  SWETZ RICHARD

    IPC: G06F11/34

    CPC classification number: H03K21/00 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  H03K23/42

    Abstract: There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated "pre-counter" while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the "sweeper" state machine accesses the pre-counter.

    Abstract translation: 这里广泛地考虑了一种安排，其中每个事件源提供一个小的专用“预计数器”，而实际的计数保存在64位宽的RAM中。 这样的实施方式优选地可以包括以预定的固定顺序简单地扫过预计数器的状态机。 优选地，状态机将访问每个预计数器，将来自预计数器的值添加到相应的RAM位置，然后清除预计数器。 因此，预计数器只需要足够宽，使得即使在最大事件速率下，在“清扫器”状态机访问预先计数器之前，预计数器将不能够包装（即达到容量或溢出） 计数器。

    Fibre channel input/output data routing system and method
    3.
    发明专利
    Fibre channel input/output data routing system and method 未知

    公开(公告)号：GB2491440B

    公开(公告)日：2013-05-15

    申请号：GB201206684

    申请日：2012-04-17

    Applicant: IBM

    Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON ,  BENDER CARL ALFRED

    IPC: G06F13/12 ,  H04L69/40

    Abstract: A computer program product is provided for performing input/output (I/O) processing. The computer program product is configured to perform: generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data discard field; generating an address control structure specifying a local channel memory location of a corresponding ACW; receiving one or more data transfer requests from a network interface that each corresponding address control structure information; accessing an ACW and routing the data transfer request to a host memory location specified in the ACW; and responsive to encountering an error during at least one of the accessing and the routing, discarding the one or more data transfer requests and setting the data discard field to a value configured to instruct a channel to discard any subsequent data transfer requests associated with the ACW.

    Fibre channel input/output data routing system and method.
    4.
    发明专利
    Fibre channel input/output data routing system and method. 未知

    公开(公告)号：GB2491440A

    公开(公告)日：2012-12-05

    申请号：GB201206684

    申请日：2012-04-17

    Applicant: IBM

    Inventor： CASPER DANIEL FRANCIS ,  FLANAGAN JOHN R ,  BUBB CLINTON ,  BENDER CARL ALFRED

    IPC: G06F13/12

    Abstract: A method for performing an input/output (I/O) operation between a host computer (102) and control-unit (118) comprises obtaining information about the I/O operation from a channel subsystem (128) in the host system, the channel having a local processor and memory. An Address Control Word (ACW) (Fig 11) is generated and specifying the memory location and having a data discard field (264, Fig 11). An address control structure (Fig 5) for each data transfer in the I/O operation is generated and forwarded to the network interface between the channel subsystem and I/O device and specifies a location in the local memory of the ACW. On receipt of an I/O command message via the network a data transfer request from the network interface is issued and includes addressing information and the corresponding ACW is accessed retrieved and used to route the data transfer request to the host memory (106) specified in the ACW. In response to an error during the accessing or the routing, the transfer is discarded and the data discard field is configured to instruct the channel to discard any subsequent data transfer requests associated with the ACW.

    Avoiding non-posted request deadlocks in devices
    6.
    发明专利
    Avoiding non-posted request deadlocks in devices 未知

    公开(公告)号：GB2503632A

    公开(公告)日：2014-01-01

    申请号：GB201319270

    申请日：2012-05-09

    Applicant: IBM

    Inventor： HANSCOM JEFFREY CHARLES ,  BENDER CARL ALFRED ,  NEEDHAM THOMAS

    IPC: G06F13/364 ,  G06F13/40

    Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

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