公开(公告)号：DE1270106B

公开(公告)日：1968-06-12

申请号：DE1270106

申请日：1962-12-18

Applicant: IBM

Inventor： BESPALKO STEPHEN ,  LAMB ESTOL C ,  SCHAFFER WALTER S

IPC: G06F3/06 ,  G06F9/355 ,  H03M1/00 ,  H03M5/00

Abstract: 976, 204. Digital data stores. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 5, 1962 [Dec. 28, 1961], No. 45894/62. Heading G4C. A multi-bit character read photo-electrically from a punched tape 12 is stored in register 25, and selected groups of bits are read out from this register sequentially, these groups of bits being used to address a store which contains representations of the tape characters in 1, 2, 4, 8, A, B, C code at the corresponding addresses. If,as shown, the tape characters have less than eight bits, 1's are entered in the spare positions (6, 7, 8) of register 25. A timing circuit gates out the bit groups 7, 8; 4-6; 1-3; in sequence to register 40, a check bit being added by generator 35. Each address character is read out from register 40 bit by bit before the next one is entered, and is transferred in turn to a magnetic core matrix store 11. An address register 80 is then used to address the store (not shown) containing the recoded representation of the character. The address may be modified by means of a singlecharacter adder 90 which adds to each address character delivered by register 40, the corresponding one of three characters stored in modifier register 91.

公开(公告)号：CA719775A

公开(公告)日：1965-10-12

申请号：CA719775D

Applicant: IBM

Inventor： LAMB ESTOL C ,  BESPALKO STEPHEN ,  SCHAFFER WALTER S

公开(公告)号：CA710448A

公开(公告)日：1965-05-25

申请号：CA710448D

Applicant: IBM

Inventor： KLOTZ RAYMOND J ,  EVANS JAMES R ,  BESPALKO STEPHEN

公开(公告)号：DE1424404A1

公开(公告)日：1969-02-13

申请号：DE1424404

申请日：1961-03-18

Applicant: IBM

Inventor： BESPALKO STEPHEN ,  RICHARD ENDICOTT EVANS JAMES ,  JOSEPH KLOTZ RAYMOND

IPC: G06F13/16 ,  G06F13/04

Abstract: 920,912. Electronic digital computors. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 21, 1961 [March 21, 1960], No. 10208/61. Class 106 (1). Where a number of data input/output facilities, such as transducer arms 10 to 12 of a multidisc random access store 41, 42, 44, are associated with a data processing machine, an instruction asking for any available facility causes (a) an examination of the state of reservation latches, one for each facility which if set indicates that its associated facility is busy, and (b) the entry in the instruction register 14 of the address of an available facility, or, when all are busy, the initiation of a new instruction cycle. The instruction may alternatively ask for a particular facility and if this is busy a new instruction cycle is started. In instruction register 14, digit 4 specifies one out of three transducer arms 10 to 12 associated with each set of storage discs 41, 42 and 44, digit 5 specifies a set of discs, digits 6 and 7 specify a disc and digits 8 and 9 specify a track of a disc. Digit 4 may also specify " free access," i.e. any available arm. At times C1 and C2 of a cycle the reservation latches are examined, at time C3 the address of an available arm is written in the digit 4 position of register 14 and in periods C5 to C10 the selection of the free arm takes place. The detailed reservation control circuits 24, in which priority is given to arm 10 over arm 11, the arm 11 over arm 12, are described with reference to Figs. 2a and 2b (not shown).