公开(公告)号：US3262100A

公开(公告)日：1966-07-19

申请号：US16271061

申请日：1961-12-28

Applicant: IBM

Inventor： STEPHEN BESPALKO ,  LAMB ESTOL C ,  SCHAFFER WALTER S

IPC: G06F3/06 ,  G06F9/355 ,  H03M1/00 ,  H03M5/00

CPC classification number: G06F9/355 ,  G06F3/06 ,  H03M1/00 ,  H03M1/18 ,  H03M5/00

公开(公告)号：US3268875A

公开(公告)日：1966-08-23

申请号：US33203963

申请日：1963-12-20

Applicant: IBM

Inventor： SCHAFFER WALTER S

IPC: H03M1/00 ,  H03M7/00

CPC classification number: H03M1/00 ,  H03M1/0617 ,  H03M7/00

公开(公告)号：CA888959A

公开(公告)日：1971-12-21

申请号：CA888959D

Applicant: IBM

Inventor： SCHAFFER WALTER S ,  LAMB ESTOL C

公开(公告)号：CA719775A

公开(公告)日：1965-10-12

申请号：CA719775D

Applicant: IBM

Inventor： LAMB ESTOL C ,  BESPALKO STEPHEN ,  SCHAFFER WALTER S

公开(公告)号：CA1000409A

公开(公告)日：1976-11-23

申请号：CA144645

申请日：1972-06-14

Applicant: IBM

Inventor： BROOKS EVERETT G ,  HARRIS EDWARD R ,  KISCADEN RICHARD C ,  SCHAFFER WALTER S ,  SOLTIS FRANK G ,  ZIMMERMAN DEAN O

IPC: G06F9/40

公开(公告)号：CA827315A

公开(公告)日：1969-11-11

申请号：CA827315D

Applicant: IBM

Inventor： SCHAFFER WALTER S

公开(公告)号：DE1270106B

公开(公告)日：1968-06-12

申请号：DE1270106

申请日：1962-12-18

Applicant: IBM

Inventor： BESPALKO STEPHEN ,  LAMB ESTOL C ,  SCHAFFER WALTER S

IPC: G06F3/06 ,  G06F9/355 ,  H03M1/00 ,  H03M5/00

Abstract: 976, 204. Digital data stores. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 5, 1962 [Dec. 28, 1961], No. 45894/62. Heading G4C. A multi-bit character read photo-electrically from a punched tape 12 is stored in register 25, and selected groups of bits are read out from this register sequentially, these groups of bits being used to address a store which contains representations of the tape characters in 1, 2, 4, 8, A, B, C code at the corresponding addresses. If,as shown, the tape characters have less than eight bits, 1's are entered in the spare positions (6, 7, 8) of register 25. A timing circuit gates out the bit groups 7, 8; 4-6; 1-3; in sequence to register 40, a check bit being added by generator 35. Each address character is read out from register 40 bit by bit before the next one is entered, and is transferred in turn to a magnetic core matrix store 11. An address register 80 is then used to address the store (not shown) containing the recoded representation of the character. The address may be modified by means of a singlecharacter adder 90 which adds to each address character delivered by register 40, the corresponding one of three characters stored in modifier register 91.