公开(公告)号：JP2006309757A

公开(公告)日：2006-11-09

申请号：JP2006117455

申请日：2006-04-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BLACKMON HERMAN L ,  HILLIER PHILIP R III ,  KIRSCHT JOSEPH A ,  VANDERPOOL BRIAN T

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F9/3824 ,  G06F13/1642

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for selecting proper timing for sending a write command to a memory.
SOLUTION: The oldest command in a write queue not colliding with a conflict queue is sent to the memory, and if a part or the whole of the following conditions are true, the command is added to the conflict queue. The conditions are the followings: all the commands in a read queue collide with the conflict queue, no read command incoming from a processor does not collide with the write queue, the number of commands in the write queue is larger than a first threshold value, and all the commands in the conflict queue exist for less than a second threshold. If the command does not access a cache line in the same memory as the command in the queue, no collision with the queue is caused. In this way, the write command is sent to the memory when influence on execution of the read command is reduced.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于选择用于向存储器发送写命令的适当定时的方法和装置。

解决方案：写入队列中与冲突队列不冲突的最早的命令将发送到内存，如果以下条件的一部分或全部为真，则将该命令添加到冲突队列中。 条件如下：读队列中的所有命令与冲突队列冲突，从处理器传入的读命令不与写队列冲突，写队列中的命令数大于第一阈值， 并且冲突队列中的所有命令都存在少于第二个阈值。 如果命令不与队列中的命令访问同一个内存中的缓存行，则不会引起与队列的冲突。 以这种方式，当读取命令的执行受到影响时，写入命令被发送到存储器。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：CA2142028A1

公开(公告)日：1995-10-02

申请号：CA2142028

申请日：1995-02-07

Applicant: IBM

Inventor： BLACKMON HERMAN L ,  DREHMEL ROBERT A ,  GROSBACH LYLE E ,  HASELHORST KENT H ,  KROLAK DAVID J ,  MARCELLA JAMES A ,  PAULSON PEDER J

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/36

Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimumnumber of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.