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    1.
    发明专利
    未知

    公开(公告)号：DE2825443A1

    公开(公告)日：1979-01-11

    申请号：DE2825443

    申请日：1978-06-09

    Applicant: IBM

    Inventor： BLASER EUGENE MARTIN ,  CONRAD DONALD ADELBERT

    IPC: H01L29/78 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/173 ,  H03K19/08

    Abstract: Disclosed is a field effect transistor (FET) logic circuit which advantageously combines enhancement and depletion mode field effect transistors. A depletion mode input transistor is connected between an input node and an intermediate node and has its gating electrode connected to a fixed potential such as ground. A self-biased depletion mode field effect load transistor is connected between a positive potential and the same intermediate node to which the gating electrode of one or more enhancement mode field effect transistors are also connected. The source electrodes of the enhancement mode field effect transistors are connected to a fixed source of potential such as ground while the drain electrodes of the enhancement mode field effect transistors provide open drain outputs to similarly constructed subsequent logic stages. A number of these open drain logic outputs may be connected together to form DOT logic configurations and the potential swing at these open drain outputs, being a function of the threshold voltage of the subsequent stage input device, is substantially less than the potential difference between the fixed positive and ground supply potentials.

    LOW POWER CLOCK GENERATOR
    2.
    发明专利
    LOW POWER CLOCK GENERATOR 未知

    公开(公告)号：DE3374161D1

    公开(公告)日：1987-11-26

    申请号：DE3374161

    申请日：1983-11-03

    Applicant: IBM

    Inventor： BLASER EUGENE MARTIN ,  CHUNG PAUL WING-SHING ,  VARSHNEY RAMESH C

    IPC: H03K5/02 ,  H03K17/06 ,  H03K19/017 ,  H03K19/094

    Abstract: A clock generator circuit for producing with very little power dissipation an output clock signal (Φ 1 ) having levels determined by positive and negative power supply levels (V DD , Vsx) from an input clock signal (Φ 1 ) having levels determined by the positive power supply level (V DD ) and ground. In a low state of the input clock signal (Φ 1 ), a first transistor (42) of an output transistor pair (42, 43) connected in series between positive and negative power supply levels (V oo , V sx ) is turned off by applying a ground level to the base thereof, while the second transistor (43) of the output transistor pair (42, 43) is turned off by applying a positive potential to its base. When the input clock signal (Φ 1 ) makes a transition from the low state to the high state, a bootstrap capacitor (39) is charged between the positive and negative power supply levels (V DD , V sx ) to provide a boosted positive voltage to turn on the first transistor (42). While the bootstrap capacitor (39) is charging, the base of the second transistor (43) is lightly grounded to partially turn it on. When the charge on the bootstrap capacitor (39) has reached a predetermined level, the base of the first transistor (42) is taken to the negative power supply level (V sx ) through an inverting transistor (36), the base of which also receives the boosted voltage developed across the bootstrap capacitor (39). By using a fully dynamic circuit arrangement, only a very small amount of power is required for operating the circuit.

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