公开(公告)号：DE3374161D1

公开(公告)日：1987-11-26

申请号：DE3374161

申请日：1983-11-03

Applicant: IBM

Inventor： BLASER EUGENE MARTIN ,  CHUNG PAUL WING-SHING ,  VARSHNEY RAMESH C

IPC: H03K5/02 ,  H03K17/06 ,  H03K19/017 ,  H03K19/094

Abstract: A clock generator circuit for producing with very little power dissipation an output clock signal (Φ 1 ) having levels determined by positive and negative power supply levels (V DD , Vsx) from an input clock signal (Φ 1 ) having levels determined by the positive power supply level (V DD ) and ground. In a low state of the input clock signal (Φ 1 ), a first transistor (42) of an output transistor pair (42, 43) connected in series between positive and negative power supply levels (V oo , V sx ) is turned off by applying a ground level to the base thereof, while the second transistor (43) of the output transistor pair (42, 43) is turned off by applying a positive potential to its base. When the input clock signal (Φ 1 ) makes a transition from the low state to the high state, a bootstrap capacitor (39) is charged between the positive and negative power supply levels (V DD , V sx ) to provide a boosted positive voltage to turn on the first transistor (42). While the bootstrap capacitor (39) is charging, the base of the second transistor (43) is lightly grounded to partially turn it on. When the charge on the bootstrap capacitor (39) has reached a predetermined level, the base of the first transistor (42) is taken to the negative power supply level (V sx ) through an inverting transistor (36), the base of which also receives the boosted voltage developed across the bootstrap capacitor (39). By using a fully dynamic circuit arrangement, only a very small amount of power is required for operating the circuit.

公开(公告)号：DE3585932D1

公开(公告)日：1992-06-04

申请号：DE3585932

申请日：1985-05-10

Applicant: IBM

Inventor： CHUNG PAUL WING-SHING ,  MATICK RICHARD EDWARD ,  LING DANIEL TAJEN

IPC: G11C11/401 ,  G06F12/00 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/00 ,  G11C11/409

Abstract: A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.