公开(公告)号：US3705419A

公开(公告)日：1972-12-05

申请号：US3705419D

申请日：1971-12-20

Applicant: IBM

Inventor： BLEHER JOHANNES HARTMUT ,  CHANG CHI SHIH ,  DOCKERTY ROBERT CHARLES

IPC: H01L21/8247 ,  H01L21/00 ,  H01L27/10 ,  H01L29/74 ,  H01L29/788 ,  H01L29/792 ,  H01L19/00

CPC classification number: H01L27/10 ,  H01L21/00 ,  Y10S257/926

Abstract: A high density memory cell comprising a silicon gate field effect transistor and a bismuth-niobium oxide-niobium bistable switching diode integrally formed over the drain electrode of the FET. The memory cell is formed by providing an oxidized P silicon wafer, stripping the oxide from the source, drain and gate region of the FET and regrowing the gate oxide. Polycrystalline silicon is deposited on the regrown gate oxide and the polysilicon is subtractively etched to delineate the gate electrode. Source and drain openings are etched using the remaining polysilicon as part of the etchant mask. An N+ diffusion is made to form the source and drain region and to dope the polycrystalline silicon FET gate electrode. The device is reoxidized and contact holes are opened to the source and drain region. Platinum-silicon is used to form the source and drain ohmic contacts. Niobium is deposited and subtractively etched except over the drain contact. Niobium oxide is formed by a wet anodizing step. Bismuth is deposited and subtractively etched except on the niobium oxide. Aluminum is deposited and subtractively etched to provide conducting pathways for contacting the source and the bismuth electrodes of the memory cell.