公开(公告)号：US3705419A

公开(公告)日：1972-12-05

申请号：US3705419D

申请日：1971-12-20

Applicant: IBM

Inventor： BLEHER JOHANNES HARTMUT ,  CHANG CHI SHIH ,  DOCKERTY ROBERT CHARLES

IPC: H01L21/8247 ,  H01L21/00 ,  H01L27/10 ,  H01L29/74 ,  H01L29/788 ,  H01L29/792 ,  H01L19/00

CPC classification number: H01L27/10 ,  H01L21/00 ,  Y10S257/926

Abstract: A high density memory cell comprising a silicon gate field effect transistor and a bismuth-niobium oxide-niobium bistable switching diode integrally formed over the drain electrode of the FET. The memory cell is formed by providing an oxidized P silicon wafer, stripping the oxide from the source, drain and gate region of the FET and regrowing the gate oxide. Polycrystalline silicon is deposited on the regrown gate oxide and the polysilicon is subtractively etched to delineate the gate electrode. Source and drain openings are etched using the remaining polysilicon as part of the etchant mask. An N+ diffusion is made to form the source and drain region and to dope the polycrystalline silicon FET gate electrode. The device is reoxidized and contact holes are opened to the source and drain region. Platinum-silicon is used to form the source and drain ohmic contacts. Niobium is deposited and subtractively etched except over the drain contact. Niobium oxide is formed by a wet anodizing step. Bismuth is deposited and subtractively etched except on the niobium oxide. Aluminum is deposited and subtractively etched to provide conducting pathways for contacting the source and the bismuth electrodes of the memory cell.

公开(公告)号：JPH1092983A

公开(公告)日：1998-04-10

申请号：JP19097497

申请日：1997-07-16

Applicant: IBM

Inventor： DOCKERTY ROBERT CHARLES ,  FRAGA RONALD MAURICE ,  RAMIREZ CIRO NEAL ,  RAY SUDIPTA KUMAR ,  ROBBINS GORDON JAY

IPC: H05K7/20 ,  H01L23/12 ,  H01L23/32 ,  H01L23/40 ,  H01L23/498 ,  H05K3/34 ,  H05K3/36

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for enhancing solder column grid array joint of a ceramic substrate to a printed circuit board. SOLUTION: A significantly large solder column 14 is formed along the periphery of a substrate simultaneously with an array of fine electric interconnection solder columns 7 on the substrate. Reinforcing columns and electrical signal columns are positioned and jointed, by solder reflow, to corresponding patterns of pads 4, 16 on a printed circuit board 6. A heat sink 9 is connected thermally with a structural element of the substrate 1 through bonding or mechanical pressing. According to the structure, stress to be generated in the solder column 14 due to bending induced by the pressing force of the heat sink 9 or vibration can be reduced significantly without requiring any complicated or special manufacturing process additionally.

公开(公告)号：DE3277265D1

公开(公告)日：1987-10-15

申请号：DE3277265

申请日：1982-12-27

Applicant: IBM

Inventor： DOCKERTY ROBERT CHARLES

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/76 ,  H01L21/82 ,  H01L27/08

公开(公告)号：DE2644832A1

公开(公告)日：1977-06-02

申请号：DE2644832

申请日：1976-10-05

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  DOCKERTY ROBERT CHARLES

IPC: H01L21/283 ,  H01L21/28 ,  H01L21/314 ,  H01L21/76 ,  H01L21/8247 ,  H01L29/41 ,  H01L29/43 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/04

Abstract: An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a conductive silicon dioxide layer disposed over the substrate. The improvement comprises forming a layer of highly resistive, silicon dioxide or silicon oxynitride, which is between the conductive oxide and the silicon nitride layer which forms a portion of the gate insulator for the field effect transistor.

公开(公告)号：FR2307334A1

公开(公告)日：1976-11-05

申请号：FR7534738

申请日：1975-11-07

Applicant: IBM

Inventor： ABRAS SHAKIR AHMED ,  DOCKERTY ROBERT CHARLES

IPC: G11C17/00 ,  G11C11/22 ,  G11C11/34 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

Abstract: A non-volatile read mostly memory cell in a monocrystalline semiconductor body wherein the sensing of the information is achieved by measuring the substrate current. The cell includes spaced source and drain regions, a gate dielectric layer capable of trapping a charge, a substrate contact electrode; a means to induce a trapped charge into the gate dielectric layer, including a means to apply a voltage larger than the threshold voltage to the gate electrode to form an inversion layer, and a means to apply a voltage to the drain electrode causing channel current to flow; a means to remove the trapped charge, including a means to apply a voltage equal to or exceeding the avalanche voltage to the drain to cause avalanching; a means to determine the presence or absence of a charge in the gate dielectric including a means to apply a voltage to the gate which is larger than the threshold voltage and a voltage to the drain that is significantly less than the avalanche voltage, and a means to determine the substrate current.

公开(公告)号：DE3277664D1

公开(公告)日：1987-12-17

申请号：DE3277664

申请日：1982-12-27

Applicant: IBM

Inventor： DE LA MONEDA FRANCISCO HOMERO ,  DOCKERTY ROBERT CHARLES

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/088 ,  H01L27/112 ,  H01L29/78 ,  H01L21/82 ,  H01L21/76 ,  H01L27/08

Abstract: For forming field effect transistors, a multilayer structure (16, 20, 21, 22, 24, 26) of different materials including a conductive layer (20) is deposited over a substrate (10). Vertical sidewalls are obtained by etching the top layers (24, 26) and a sidewall layer (30) is formed by oxidizing the sidewalls. Removing further material leaves the very fine structure of sidewall layers, which is used as a mask to etch the lower layers (22, 21, 20) so as to leave portions of the conductive layer as very fine gate electrodes, plus interconnections. Some gate electrodes of larger dimension are obtained simultaneously by covering the area between two stripes of the sidewall layer before etching down to the conductive layer.

公开(公告)号：DE2611158A1

公开(公告)日：1976-10-28

申请号：DE2611158

申请日：1976-03-17

Applicant: IBM

Inventor： ABBAS SHAKIR AHMED ,  DOCKERTY ROBERT CHARLES ,  POPONIAK MICHAEL ROBERT

IPC: H01L21/306 ,  H01L21/3063 ,  H01L21/308 ,  B28D5/06

Abstract: 1515031 Electrolytic etching of silicon INTERNATIONAL BUSINESS MACHINES CORP 3 Feb 1976 [14 April 1975] 4111/76 Heading C7B [Also in Division H1] A hole is made in a monocrystalline silicon body by providing masking with aligned apertures on parallel opposed faces of the body, providing a conductor in contact with the body through one of the openings and using this as anode in an anodic treatment to convert the entire region between the apertures to porous silicon which is then etched out to leave a hole. Typically a plurality of holes are simultaneously formed in a 100 oriented wafer which may have integrated circuitry formed on one or both faces. The masking may consist of silicon dioxide or nitride with an optical overlayer of chromium, or of silicon oxynitride or nitride-onoxide. After photoetching to form the apertures heavily doped surface regions may be formed below the apertures on one or both faces by impurity diffusion or implantation of helium ions or protons and a chromium anode layer deposited on one face. After anodic treatment in a 1:2 mixture of 49% hydrofluoric acid and distilled water the anode is removed and the porous silicon etched out.

公开(公告)号：DE2355605A1

公开(公告)日：1974-06-12

申请号：DE2355605

申请日：1973-11-07

Applicant: IBM

Inventor： BARILE CONRAD ALBERT ,  DOCKERTY ROBERT CHARLES ,  NAGARAJAN ARUNACHALA

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L29/00 ,  H01L29/51 ,  H01L7/34 ,  H01L1/10

Abstract: Large threshold voltage shifts of silicon gate FET devices having a composite nitride-oxide gate dielectric are greatly reduced by subjecting the nitride to a dry oxygen annealing at temperatures between 970 DEG -1,150 DEG C prior to depositing the silicon gate electrode. Annealing at 1,050 DEG C applied for a duration of one-half to one hour produces excellent results.

公开(公告)号：MY116990A

公开(公告)日：2004-04-30

申请号：MYPI9704897

申请日：1997-10-17

Applicant: IBM

Inventor： DOCKERTY ROBERT CHARLES ,  FRAGA RONALD MAURICE ,  RAMIREZ CIRO NEAL ,  RAY SUDIPTA KUMAR ,  REYNOLDS CHARLES LEVERN JR ,  ROBBINS GORDON JAY

IPC: H01L23/48 ,  H01L21/60 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34

Abstract: SUPPORTING STRUCTURE FOR A BAL1 GRID ARRAY SURFACE MOUNTED INTEGRATED CIRCUIT DEVICE (3, 24, 26) COMPOSED OF SUPPORT SOLDER (6, 16-18, 33) FORMED AT SELECTIVE CORNER LOCATIONS (19, 31, 32) ON THE BALL GRID ARRAY SURFACE OF THE INTEGRATED CIRCUIT DEVICE. IN ONE FORM, L-SHAPED PATTERNS OF HIGH MELTING TEMPERATURE SOLDER ARE FORMED ALONG THE AXES DEFINED BY THE BALL GRID ARRAY AND ARE CHARACTERIZED IN THAT CROSS SECTIONS OF THE L-SHAPED PATTERN MATCH THAT OF THE SOLDER BALLS ALONG ONE AXIS, AND REPRESENT A CONTINUUM OF SOLDER BETWEEN SOLDER BALL LOCATIONS ALONG THE OTHER AXIS. SUPPORT SOLDER CAN BE ADDED WHERE NECESSARY TO PROVIDE BOTH STRUCTURAL REINFORCEMENT AND THERMAL CONDUCTION. CONTROL OF THE CROSS SECTION OF THE SUPPORT SOLDER ENSURES THAT SURFACE TENSION EFFECTS OF THE MOLTEN LOW TEMPERATURE REFLOW SOLDER (12, 29) USED TO CONNECT THEINTEGRATED CIRCUIT DEVICE DOES NOT MATERIAL1Y CHANGE THE FINAL RELATIVE SPACING BETWEEN THE INTEGRATED CIRCUIT DEVICE BALLS (11) AND THE UNDERLYING PRINTED CIRCUIT BOARD CONTACTS (2).

公开(公告)号：DE69721148D1

公开(公告)日：2003-05-28

申请号：DE69721148

申请日：1997-07-09

Applicant: IBM

Inventor： DOCKERTY ROBERT CHARLES ,  FRAGA RONALD MAURICE ,  RAMIREZ CIRO NEAL ,  RAY SUDIPTA KUMAR ,  ROBBINS GORDON JAY

IPC: H05K7/20 ,  H01L23/12 ,  H01L23/32 ,  H01L23/40 ,  H01L23/498 ,  H05K3/34 ,  H05K3/36

Abstract: Structure and method for reinforcing a solder column grid array attachment of a ceramic or the like substrate to a printed circuit board, the reinforcement providing support for a heat sink which is bonded or affixed by pressure to a structural element of the substrate. In one form, the invention involves the concurrent formation of materially larger solder columns along the perimeter of the substrate in conjunction with the array of thin electrically interconnecting solder columns on the substrate. The reinforcing and electrical signal columns are thereafter aligned and attached by solder reflow to a corresponding pattern of pads on the printed circuit board. The heat sink is thermally connected to a structural element of the substrate by bonding or mechanical compression. Stresses in the solder columns caused by heat sink compressive forces or vibration induced flexing are materially decreased without adding complex or unique manufacturing operations.