公开(公告)号：BR8600788A

公开(公告)日：1986-11-04

申请号：BR8600788

申请日：1986-02-25

Applicant: IBM

Inventor： BLEVINS BALLARD JOHN ,  KULPA WILLIAM GARRY ,  MATHIS JOSEPH RICHARD ,  MCCULLOUGH JOHN WARREN

IPC: G06F13/36 ,  G06F12/06

Abstract: Bus-to-bus converter (8) in a data processing system comprising a system bus (6) connecting a system storage unit to a central processing unit, said converter (8) connecting the system bus (6) to an I/O bus (10) to which are attached a plurality of randomly selected I/O devices. The converter (8) dynamically inserts appropriate address control information into messages transmitted from the I/O bus (10) to the system bus (6), whereby access can be denied to and from selected I/O devices.

公开(公告)号：BR8700436A

公开(公告)日：1987-12-15

申请号：BR8700436

申请日：1987-01-30

Applicant: IBM

Inventor： BLEVINS BALLARD JOHN ,  KULPA WILLIAM GARY ,  MATHIS JOSEPH RICHARD

IPC: G06F15/16 ,  G06F13/38 ,  G06F15/17 ,  G06F15/177 ,  G06F13/00

Abstract: In a multiprocessor data processing system, the sequential access portion (31b) of a memory (31) associated with one processor (P1) is connected to the sequential access portion (41b) of a memory (41) associated with another processor (P2) in such a way, via driver/receivers (34, 44) and a channel (51a), that data can flow between the sequential access portions asynchronously of the remainder of the system. Each of the memories (31, 41) also comprises a random access portion (31a, 41a) which is accessible by its associated processor via a conventional random access port and means to transfer data between its random access portion and its sequential access portion. Data flow operations between the sequential access portions of the memories is controlled by control means (32, 42) connected to the channel and via system buses (33, 43) to the processors (P1, P2).