公开(公告)号：DE69027868T2

公开(公告)日：1997-02-06

申请号：DE69027868

申请日：1990-01-10

Applicant: IBM

Inventor： MATHIS JOSEPH RICHARD ,  OEHLER RICHARD RAPHAEL ,  ZEITLER CARL

IPC: G06F13/12

Abstract: The invention relates to a data processing system comprising a processor means (2) for issuing communications commands on a first communications channel (4), a peripheral means (5, 6, 7) connected to the first communications channel and to a second communications channel (8) operating asynchronously, for performing operations specified by commands from the processor means and for responding to communications on the second communications channel, and status indicating means for indicating to the processor means the status of the peripheral means. According to the invention the data processing system is characterised in that the status indicating means comprises control means for providing a status word to the processor means in response to a command issued to the peripheral means by the processor means, the status word indicating the status of the peripheral means at a time when the peripheral means initiates an operation specified by the issued command.

公开(公告)号：DE69027342T2

公开(公告)日：1996-12-05

申请号：DE69027342

申请日：1990-01-10

Applicant: IBM

Inventor： MATHIS JOSEPH RICHARD ,  ROUSE GERALD LAVELLE

IPC: H04L29/08 ,  H04L29/06

Abstract: The present invention relates to a two-directional data communications system comprising a first device (12) for transmitting and receiving data, a second device (14) for transmitting and receiving data, and communications links (16, 18) coupled to the first and second devices for transferring data therebetween. According to the invention the communications system is characterised in that the first device comprises means for establishing a communications link over the communications system and for subsequently transferring data to the second device over the link and the second device comprises means for transferring, using the same communications link, a data transfer direction turnaround message to the first device and means for subsequently transferring data to the first device.

公开(公告)号：BR8700435A

公开(公告)日：1987-12-15

申请号：BR8700435

申请日：1987-01-30

Applicant: IBM

Inventor： KULPA WILLIAM GARY ,  MATHIS JOSEPH RICHARD

IPC: G06F3/153 ,  G06F13/16 ,  G06F13/38 ,  G06F13/00 ,  G06F7/00

公开(公告)号：BR8600788A

公开(公告)日：1986-11-04

申请号：BR8600788

申请日：1986-02-25

Applicant: IBM

Inventor： BLEVINS BALLARD JOHN ,  KULPA WILLIAM GARRY ,  MATHIS JOSEPH RICHARD ,  MCCULLOUGH JOHN WARREN

IPC: G06F13/36 ,  G06F12/06

Abstract: Bus-to-bus converter (8) in a data processing system comprising a system bus (6) connecting a system storage unit to a central processing unit, said converter (8) connecting the system bus (6) to an I/O bus (10) to which are attached a plurality of randomly selected I/O devices. The converter (8) dynamically inserts appropriate address control information into messages transmitted from the I/O bus (10) to the system bus (6), whereby access can be denied to and from selected I/O devices.

公开(公告)号：DE2752882A1

公开(公告)日：1978-06-22

申请号：DE2752882

申请日：1977-11-26

Applicant: IBM

Inventor： MATHIS JOSEPH RICHARD

IPC: G04F3/00 ,  G04F10/00 ,  G04F10/04 ,  G05B19/02 ,  G06F11/30 ,  G06F13/00 ,  G06F13/37 ,  G06F13/42 ,  H04Q9/00 ,  G06F1/04 ,  H04L25/02

Abstract: A composite shift register timer for controlling a sequence of events occurring over a demand-response interface. The composite shift register comprises a primary shift register and a secondary shift register. The primary shift register is divided into successive portions which are selectively coupled together in successive pairs upon timely receipt of respective response signals. A first binary "1" is inserted into the first portion at the start of a predetermined sequence of events. The first "1" is clocked through to the end of the first portion where it initiates a demand and is stored pending the receipt of a corresponding response. A second binary "1" is clocked through the secondary shift register beginning with the initiation of each demand. The clocking of the second "1" continues until the receipt of a timely response to the initiated demand whereupon the secondary shift register is reset. The timely response also is applied to the coupling means between the first and second portions of the primary shift register to permit the stored first "1" to propagate into and be clocked through the second portion. If no timely response is received, the second "1" propagates to the end of the secondary shift register to produce an "error" signal. The error signal deactivates each coupling means between the portions of the first shift register to prevent the first binary "1" from propagating any farther, thus terminating the sequence of events.

公开(公告)号：DE69027342D1

公开(公告)日：1996-07-18

申请号：DE69027342

申请日：1990-01-10

Applicant: IBM

Inventor： MATHIS JOSEPH RICHARD ,  ROUSE GERALD LAVELLE

IPC: H04L29/08 ,  H04L29/06

Abstract: The present invention relates to a two-directional data communications system comprising a first device (12) for transmitting and receiving data, a second device (14) for transmitting and receiving data, and communications links (16, 18) coupled to the first and second devices for transferring data therebetween. According to the invention the communications system is characterised in that the first device comprises means for establishing a communications link over the communications system and for subsequently transferring data to the second device over the link and the second device comprises means for transferring, using the same communications link, a data transfer direction turnaround message to the first device and means for subsequently transferring data to the first device.

公开(公告)号：DE69021899D1

公开(公告)日：1995-10-05

申请号：DE69021899

申请日：1990-01-11

Applicant: IBM

Inventor： FOGG RICHARD G ,  MATHIS JOSEPH RICHARD ,  NICHOLSON JAMES OTTO

IPC: G06F13/28

Abstract: A DMA controller is described which has an attached, dedicated memory. Data objects are stored in this memory and are linked to one another, by pointers. Each data object contains DMA block transfer control parameters. A single block transfer is made up of several separate transfers, with each separate transfer defined by one data object. The single block transfer is defined by linking several data objects into a list. The DMA controller consecutively performs the transfers in a linked list without requiring control by a system central processor.

公开(公告)号：BR8700436A

公开(公告)日：1987-12-15

申请号：BR8700436

申请日：1987-01-30

Applicant: IBM

Inventor： BLEVINS BALLARD JOHN ,  KULPA WILLIAM GARY ,  MATHIS JOSEPH RICHARD

IPC: G06F15/16 ,  G06F13/38 ,  G06F15/17 ,  G06F15/177 ,  G06F13/00

Abstract: In a multiprocessor data processing system, the sequential access portion (31b) of a memory (31) associated with one processor (P1) is connected to the sequential access portion (41b) of a memory (41) associated with another processor (P2) in such a way, via driver/receivers (34, 44) and a channel (51a), that data can flow between the sequential access portions asynchronously of the remainder of the system. Each of the memories (31, 41) also comprises a random access portion (31a, 41a) which is accessible by its associated processor via a conventional random access port and means to transfer data between its random access portion and its sequential access portion. Data flow operations between the sequential access portions of the memories is controlled by control means (32, 42) connected to the channel and via system buses (33, 43) to the processors (P1, P2).

公开(公告)号：DE69027868D1

公开(公告)日：1996-08-29

申请号：DE69027868

申请日：1990-01-10

Applicant: IBM

Inventor： MATHIS JOSEPH RICHARD ,  OEHLER RICHARD RAPHAEL ,  ZEITLER CARL

IPC: G06F13/12

Abstract: The invention relates to a data processing system comprising a processor means (2) for issuing communications commands on a first communications channel (4), a peripheral means (5, 6, 7) connected to the first communications channel and to a second communications channel (8) operating asynchronously, for performing operations specified by commands from the processor means and for responding to communications on the second communications channel, and status indicating means for indicating to the processor means the status of the peripheral means. According to the invention the data processing system is characterised in that the status indicating means comprises control means for providing a status word to the processor means in response to a command issued to the peripheral means by the processor means, the status word indicating the status of the peripheral means at a time when the peripheral means initiates an operation specified by the issued command.

公开(公告)号：DE69021899T2

公开(公告)日：1996-04-18

申请号：DE69021899

申请日：1990-01-11

Applicant: IBM

Inventor： FOGG RICHARD G ,  MATHIS JOSEPH RICHARD ,  NICHOLSON JAMES OTTO

IPC: G06F13/28

Abstract: A DMA controller is described which has an attached, dedicated memory. Data objects are stored in this memory and are linked to one another, by pointers. Each data object contains DMA block transfer control parameters. A single block transfer is made up of several separate transfers, with each separate transfer defined by one data object. The single block transfer is defined by linking several data objects into a list. The DMA controller consecutively performs the transfers in a linked list without requiring control by a system central processor.