公开(公告)号：DE3473710D1

公开(公告)日：1988-09-29

申请号：DE3473710

申请日：1984-05-21

Applicant: IBM

Inventor： BODE JAMES WALTER ,  MONTEGARI FRANK ALFRED

IPC: H03K17/04 ,  H03K17/66 ,  H03K19/00 ,  H03K19/013 ,  H03K19/082 ,  H03K19/084

Abstract: A logic circuit is disclosed which comprises two complementary transistors (T1, T2) whose bases are connected directly (J) to each other, and to the input terminals (A, B, C), via respective diodes (D1, D2, D3), and whose collectors are connected directly (I) to each other and to the output terminal (Z). Of these series-connected transistors, one (T1) has its emitter connected to a positive voltage terminal of a dc power source, and the other (T2) has its emitter connected through a parallel R-C combination (C1, R2) to ground. The bases of both transistors are connected to ground via an additional registor (R1). This logic circuit has low power dissipation and is particularly suited for performing the NOR or NAND function.