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    HIGH SPEED LOW POWER LOGIC CIRCUIT
    4.
    发明专利
    HIGH SPEED LOW POWER LOGIC CIRCUIT 未知

    公开(公告)号：DE3473710D1

    公开(公告)日：1988-09-29

    申请号：DE3473710

    申请日：1984-05-21

    Applicant: IBM

    Inventor： BODE JAMES WALTER ,  MONTEGARI FRANK ALFRED

    IPC: H03K17/04 ,  H03K17/66 ,  H03K19/00 ,  H03K19/013 ,  H03K19/082 ,  H03K19/084

    Abstract: A logic circuit is disclosed which comprises two complementary transistors (T1, T2) whose bases are connected directly (J) to each other, and to the input terminals (A, B, C), via respective diodes (D1, D2, D3), and whose collectors are connected directly (I) to each other and to the output terminal (Z). Of these series-connected transistors, one (T1) has its emitter connected to a positive voltage terminal of a dc power source, and the other (T2) has its emitter connected through a parallel R-C combination (C1, R2) to ground. The bases of both transistors are connected to ground via an additional registor (R1). This logic circuit has low power dissipation and is particularly suited for performing the NOR or NAND function.

    COMPLEMENTARY LOGIC CIRCUIT
    8.
    发明专利
    COMPLEMENTARY LOGIC CIRCUIT 未知

    公开(公告)号：DE3374368D1

    公开(公告)日：1987-12-10

    申请号：DE3374368

    申请日：1983-02-28

    Applicant: IBM

    Inventor： MONTEGARI FRANK ALFRED

    IPC: G11C11/413 ,  G11C8/10 ,  H03K19/082 ,  H03K19/084 ,  H03K19/086 ,  H03K19/21 ,  H03M7/00

    Abstract: A logic circuit having n inputs for accepting n binary inputs (X, Y) and having an output terminal for providing as an output a predetermined logical binary function (B) of said n inputs. … The logic circuit comprises n transistors (11, 12) of a first conductivity type, the bases of which form the inputs, an n + 1 transistor (2) of said first conductivity type, and an n + 2 transistor (1) of the second conductivity type. … The collectors of said n transistors (11, 12) and the emitter of said n + 2 transistor (1) are connected. … The emitters of said n transistors and the emitter of said n + 1 transistor (2) are connected. … A first resistor (3) is connected between the emitter of said n + 2 transistor (1) and a first source of potential. … A second resistor (4) is connected between the collector of said n + 1 transistor (2) and said first source of potential. … A third resistor (5) is connected between the emitter of said n + 1 transistor (2) and a third source of potential. … The collector of said n + 2 transistor (1) is connected to said third source of potential. … The base of said n + 1 transistor (2) and the base of the n + 2 transistor (1) are fed in common to a second source of potential. … The collector of said n + 1 transistor (3) forms the output of the circuit.

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