公开(公告)号：GB2523188A

公开(公告)日：2015-08-19

申请号：GB201402849

申请日：2014-02-18

Applicant: IBM

Inventor： SCHROEDER FRIEDRICH ,  BOERSMA MAARTEN ,  FUCHS THOMAS ,  LANG DAVID

IPC: G06F17/50

Abstract: An improved method and system are provided for pipeline depth exploration in a register transfer level design description of an electronic circuit. The method comprises providing a list of input registers and output registers for the circuit design to be modified S100, traversing output connections paths for each input register and replacing any register in the output connection paths by a respective wire unless the register is contained in the list of output registers S110. An initial total cycle time value for the modified registerless circuit design is determined, accounting for a register latch insertion delay time value S120. A gate level description for the modified circuit design is obtained by macro synthesis with the initial total cycle time value S130, and the total cycle time value for the modified circuit design is varied to determine theoretical limit of the modified circuit design S140. The theoretical limit of the modified circuit design is realized when negative slacks are present in the macro synthesis of the gate level description for the modified circuit design with the corresponding total cycle time value S150. The pipeline depth of the circuit design may be reduced, if said total cycle time value of the modified circuit design is lower than a threshold.