公开(公告)号：US3697980A

公开(公告)日：1972-10-10

申请号：US3697980D

申请日：1971-06-30

Applicant: IBM

Inventor： BOINODIRIS STAVROS ,  HELLWARTH GEORGE A

IPC: H03M1/00 ,  H03K13/04

CPC classification number: H03M1/74

Abstract: A digital-to-analog converter employing a pair of operational amplifiers connected in a balanced differential configuration to supply an analog output to a two-terminal load. The data and power inputs are isolated from the converter by isolation couplers. Each bit of binary data is sensed at the summing junction of each amplifier by means of a pair of balanced resistors which are switched in accordance with the binary signal. Each set of balanced resistors so sensed is in parallel with the other sets between the summing junctions. The balanced differential configuration enables either terminal at the twoterminal load to be at ground reference potential without deteriorating the common-mode rejection capability of the circuit, thereby eliminating the effect of voltages existing between the ground reference at the load and the ground reference at the binary and power input terminals of the converter.

Abstract translation: 一种数模转换器采用一对以平衡差分配置连接的运算放大器，以将模拟输出提供给双端负载。 数据和电源输入通过隔离耦合器与转换器隔离。 通过一对根据二进制信号切换的平衡电阻器，在每个放大器的求和点处感测每一位二进制数据。 如此感测的每组平衡电阻与求和点之间的其他组并联。 平衡差分配置使得两端负载中的任一端子处于接地参考电位，而不会降低电路的共模抑制能力，从而消除了存在于负载下的接地参考电压与地参考之间的电压的影响 转换器的二进制和电源输入端子。

公开(公告)号：DE2222182A1

公开(公告)日：1973-01-11

申请号：DE2222182

申请日：1972-05-05

Applicant: IBM

Inventor： HELLWARTH GEORGE ARLEN ,  BOINODIRIS STAVROS

IPC: H03M1/00 ,  H03K13/14

Abstract: A digital-to-analog converter employing a pair of operational amplifiers connected in a balanced differential configuration to supply an analog output to a two-terminal load. The data and power inputs are isolated from the converter by isolation couplers. Each bit of binary data is sensed at the summing junction of each amplifier by means of a pair of balanced resistors which are switched in accordance with the binary signal. Each set of balanced resistors so sensed is in parallel with the other sets between the summing junctions. The balanced differential configuration enables either terminal at the two-terminal load to be at ground reference potential without deteriorating the common-mode rejection capability of the circuit, thereby eliminating the effect of voltages existing between the ground reference at the load and the ground reference at the binary and power input terminals of the converter.