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    Digital fsk/psk detector
    1.
    发明授权
    Digital fsk/psk detector 失效
    数字FSK / PSK检测器

    公开(公告)号：US3571712A

    公开(公告)日：1971-03-23

    申请号：US3571712D

    申请日：1969-07-30

    Applicant: IBM

    Inventor： HELLWARTH GEORGE A ,  JONES GARDNER D JR

    IPC: H04L27/156 ,  H04L27/233 ,  H04B1/16

    CPC classification number: H04L27/1563 ,  H04L27/2331

    Abstract: The digital FSK/PSK detector demodulates digital data from a frequency shift keyed modulation signal (FSK) or a phase shift keyed modulation signal (PSK) for moderate data rates including at least 1200 bits per second and is capable of operating over switching networks. The digital FSK/PSK detector comprises a binary amplitude quantizer, a clock, a digital time quantizer, a digital delay coacting with an Exclusive-OR circuit for detecting the digital data signal from the FSK/PSK modulated signal and a digital filter and smoothing circuit for eliminating undesirable noise from the digital data signal.

    Analog to digital converter for electrical signals
    3.
    发明授权
    Analog to digital converter for electrical signals 失效
    模拟数字转换器电子信号

    公开(公告)号：US3859654A

    公开(公告)日：1975-01-07

    申请号：US29670772

    申请日：1972-10-11

    Applicant: IBM

    Inventor： HARRISON THOMAS J ,  HELLWARTH GEORGE A ,  JAEGER RICHARD C

    IPC: H03M1/50 ,  H03M1/00 ,  H03K13/20

    CPC classification number: H03M1/50

    Abstract: Unknown bipolar analog signals are converted to equivalent digital signals by comparison with positive and negative reference voltages. Sampling is performed for a preselected time period during which the reference voltages are alternately compared against the unknown analog signal. The reference polarity is switched each time the comparison result indicates a polarity change. Counting of clock pulses during all times one of the reference voltages is applied for the preselected period results in the digital equivalent of the analog input.

    Abstract translation: 与正和负参考电压相比，未知的双极模拟信号被转换为等效的数字信号。 在预选的时间段执行采样，在此期间参考电压与未知模拟信号交替地进行比较。 每次比较结果表示极性变化时，参考极性被切换。 在所有时间内对时钟脉冲进行计数，一个参考电压被施加在预选的周期，导致模拟输入的数字等效。

    Binary coded digital to analog converter
    4.
    发明授权
    Binary coded digital to analog converter 失效
    二进制数字到模拟转换器

    公开(公告)号：US3576575A

    公开(公告)日：1971-04-27

    申请号：US3576575D

    申请日：1968-11-21

    Applicant: IBM

    Inventor： HELLWARTH GEORGE A ,  JONES GARDNER D JR

    IPC: H03M1/82 ,  H03M1/00 ,  H03K13/02

    CPC classification number: H03M1/00 ,  H03M1/1066

    Abstract: Apparatus for converting binary coded digital signals into analog signals, in which the initial digital signal is at first converted into a pulse whose duration is representative of said digital signal, then integrated. Also disclosed are some improvements allowing harmonics to be reduced, more particularly by combining a first pulse whose duration is representative of the binary value of the digital signal with a second pulse whose duration is representative of the binary complement of the value of said digital signal.

    Isolated digital-to-analog converter
    7.
    发明授权
    Isolated digital-to-analog converter 失效
    隔离数字到模拟转换器

    公开(公告)号：US3697980A

    公开(公告)日：1972-10-10

    申请号：US3697980D

    申请日：1971-06-30

    Applicant: IBM

    Inventor： BOINODIRIS STAVROS ,  HELLWARTH GEORGE A

    IPC: H03M1/00 ,  H03K13/04

    CPC classification number: H03M1/74

    Abstract: A digital-to-analog converter employing a pair of operational amplifiers connected in a balanced differential configuration to supply an analog output to a two-terminal load. The data and power inputs are isolated from the converter by isolation couplers. Each bit of binary data is sensed at the summing junction of each amplifier by means of a pair of balanced resistors which are switched in accordance with the binary signal. Each set of balanced resistors so sensed is in parallel with the other sets between the summing junctions. The balanced differential configuration enables either terminal at the twoterminal load to be at ground reference potential without deteriorating the common-mode rejection capability of the circuit, thereby eliminating the effect of voltages existing between the ground reference at the load and the ground reference at the binary and power input terminals of the converter.

    Abstract translation: 一种数模转换器采用一对以平衡差分配置连接的运算放大器，以将模拟输出提供给双端负载。 数据和电源输入通过隔离耦合器与转换器隔离。 通过一对根据二进制信号切换的平衡电阻器，在每个放大器的求和点处感测每一位二进制数据。 如此感测的每组平衡电阻与求和点之间的其他组并联。 平衡差分配置使得两端负载中的任一端子处于接地参考电位，而不会降低电路的共模抑制能力，从而消除了存在于负载下的接地参考电压与地参考之间的电压的影响 转换器的二进制和电源输入端子。

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