公开(公告)号：DE3280160D1

公开(公告)日：1990-05-31

申请号：DE3280160

申请日：1982-12-02

Applicant: IBM

Inventor： BOND GEORGE LEROY ,  SATYA AKELLA VENKATA SURYA

IPC: G06F12/16 ,  G06F11/16 ,  G11C29/00 ,  G11C29/42 ,  G06F11/20

Abstract: A memory system is provided with a simple flexible control arrangement for assigning locations in an alternate memory as replacements for previously identified defective fault areas in main memory (30). The assignment of the replacement locations in the alternate memory is made on a selective basis taking into consideration the defect status of other failure independent bit positions of a data word and the power of the ECC code which is used in connection with the memory system. A relatively small writable index, which is addressed by a subset of the main memory address signals, provides a partial address and control fields to the alternate memory in accordance with control data transferred from the host system. Control data is developed by the host system each time it is powered on and is based on identifying each defective location in main memory through a diagnostic routine and analyzing the defect distribution in a way to provide control signals which minimize the number of replacements that are assigned and maximize the number of data words that can be transferred from the memory system to the host system before an uncorrectable error is encountered by the ECC system.