公开(公告)号：GB2290640A

公开(公告)日：1996-01-03

申请号：GB9510909

申请日：1995-05-30

Applicant: IBM

Inventor： BLACKLEDGE JOHN WILEY ,  BOURY BECHARA ,  VALLI RONALD

IPC: G06F13/36 ,  G06F12/06 ,  G06F13/14 ,  G06F13/40

Abstract: An information processing system includes a processor (12) having a circuit for omitting input/output (I/O) address signals within a predetermined n-bit I/O address range, and apparatus (14) for appending an additional m-bit address segment to an I/O address emitted by the processor, in response to an I/O signal from the processor, to provide an expanded I/O address space. A bus bridge (Fig. 4) is also described. If the high bits of an address fall within a predetermined range then the low bits are transmitted to another bus.