公开(公告)号：BR8801091A

公开(公告)日：1988-10-18

申请号：BR8801091

申请日：1988-03-11

Applicant: IBM

Inventor： HEATH CHESTER A ,  LANGGOOD JOHN K ,  VALLI RONALD

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

公开(公告)号：GB2290640A

公开(公告)日：1996-01-03

申请号：GB9510909

申请日：1995-05-30

Applicant: IBM

Inventor： BLACKLEDGE JOHN WILEY ,  BOURY BECHARA ,  VALLI RONALD

IPC: G06F13/36 ,  G06F12/06 ,  G06F13/14 ,  G06F13/40

Abstract: An information processing system includes a processor (12) having a circuit for omitting input/output (I/O) address signals within a predetermined n-bit I/O address range, and apparatus (14) for appending an additional m-bit address segment to an I/O address emitted by the processor, in response to an I/O signal from the processor, to provide an expanded I/O address space. A bus bridge (Fig. 4) is also described. If the high bits of an address fall within a predetermined range then the low bits are transmitted to another bus.