公开(公告)号：JPH10107065A

公开(公告)日：1998-04-24

申请号：JP21839097

申请日：1997-08-13

Applicant: IBM

Inventor： BOZSO FERENC MIKLOS ,  EMMA PHILIP GEORGE

IPC: H01L21/60 ,  G06F1/10 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/02 ,  H01L23/12 ,  H01L23/538

Abstract: PROBLEM TO BE SOLVED: To form a clock distribution network, which is intensively controllable, on a secondary substrate and to make it possible to distribute a clock signal to a primary substrate by a method wherein the primary and secondary substrates are connected with each other in opposition to each other so that I/O pacts on the secondary substrate can be accessed to a connection means on the outside of a system. SOLUTION: A primary substrate is a microprocessor chip having not a clock distribution network and the clock distribution network is provided on a secondary substrate. Accordingly, the powers of circuits, which are related to the two systems, are same. In the case where the clock distribution network only is provided on the secondary substrate, the active region of the secondary substrate is very sparse and a redrive node of a clock tree can be ideally arranged on the secondary substrate. The primary substrate and the secondary substrate are of the same degree in size in one form of practive, but the primary substrate is shifted from the secondary substrate via solder balls 600 so that I/O pins 602 for external connection use on the primary substrate and I/O pins 604 for external connection use on the secondary substrate are exposed and the primary substrate is coupled with the secondary substrate. Both of the primary and secondary substrates bear an active circuit.

公开(公告)号：DE69715762D1

公开(公告)日：2002-10-31

申请号：DE69715762

申请日：1997-07-22

Applicant: IBM

Inventor： BOZSO FERENC MIKLOS ,  EMMA PHILIP GEORGE

IPC: H01L21/60 ,  G06F1/10 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/02

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

公开(公告)号：HK1006242A1

公开(公告)日：1999-02-19

申请号：HK98105470

申请日：1998-06-17

Applicant: IBM

Inventor： BOZSO FERENC MIKLOS ,  EMMA PHILIP GEORGE

IPC: H01L21/60 ,  G06F1/10 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/02 ,  H01L

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

公开(公告)号：MY117458A

公开(公告)日：2004-06-30

申请号：MYPI9703236

申请日：1997-07-16

Applicant: IBM

Inventor： BOZSO FERENC MIKLOS ,  EMMA PHILIP GEORGE

IPC: H01L21/60 ,  G06F1/10 ,  H01L23/48 ,  H01L21/44 ,  H01L21/48 ,  H01L23/02 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/02 ,  H01L29/40

Abstract: A PRECISE AND HIGHLY CONTROLLABLE CLOCK-DISTRIBUTION NETWORK IS PROVIDED ON ONE ACTIVE, SUBSTRATE (802) TO DISTRIBUTE CLOCK SIGNALS WITH MINIMAL SKEW TO ANOTHER ACTIVE SUBSTRATE (800) BY CONNECTING THE SUBSTRATES TOGETHER FACE-TO-FACE USING FLIP-CHIP TECHNOLOGY (806). SINCE THE CLOCK-DISTRIBUTION SUBSTRATE IS SPARSE, "QUIET BUSSES" ARE PROVIDED ON THE SPARSE SUBSTRATE TO FACILITATE THE HIGH-SPEED TRANSFER OF DATA OVER RELATIVELY LONG DISTANCES. LOW-POWER DEVICES (E.G., DRAM) CAN BE PROVIDED ON ONE SUBSTRATE (802) FOR USE BY HIGHER-POWER LOGIC (E.G., A PROCESSOR) ON ANOTHER SUBSTRATE (800) WITH MINIMAL INTERCONNECTION DISTANCE.

公开(公告)号：DE69715762T2

公开(公告)日：2003-04-24

申请号：DE69715762

申请日：1997-07-22

Applicant: IBM

Inventor： BOZSO FERENC MIKLOS ,  EMMA PHILIP GEORGE

IPC: H01L21/60 ,  G06F1/10 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/02

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

公开(公告)号：SG53009A1

公开(公告)日：1998-09-28

申请号：SG1997002395

申请日：1997-07-07

Applicant: IBM

Inventor： BOZSO FERENC MIKLOS ,  EMMA PHILIP GEORGE

IPC: G06F1/10 ,  H01L23/52 ,  H01L21/60 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/02 ,  H01L21/311

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.