公开(公告)号：JPH10107065A

公开(公告)日：1998-04-24

申请号：JP21839097

申请日：1997-08-13

Applicant: IBM

Inventor： BOZSO FERENC MIKLOS ,  EMMA PHILIP GEORGE

IPC: H01L21/60 ,  G06F1/10 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/02 ,  H01L23/12 ,  H01L23/538

Abstract: PROBLEM TO BE SOLVED: To form a clock distribution network, which is intensively controllable, on a secondary substrate and to make it possible to distribute a clock signal to a primary substrate by a method wherein the primary and secondary substrates are connected with each other in opposition to each other so that I/O pacts on the secondary substrate can be accessed to a connection means on the outside of a system. SOLUTION: A primary substrate is a microprocessor chip having not a clock distribution network and the clock distribution network is provided on a secondary substrate. Accordingly, the powers of circuits, which are related to the two systems, are same. In the case where the clock distribution network only is provided on the secondary substrate, the active region of the secondary substrate is very sparse and a redrive node of a clock tree can be ideally arranged on the secondary substrate. The primary substrate and the secondary substrate are of the same degree in size in one form of practive, but the primary substrate is shifted from the secondary substrate via solder balls 600 so that I/O pins 602 for external connection use on the primary substrate and I/O pins 604 for external connection use on the secondary substrate are exposed and the primary substrate is coupled with the secondary substrate. Both of the primary and secondary substrates bear an active circuit.

公开(公告)号：JP2000114453A

公开(公告)日：2000-04-21

申请号：JP27273198

申请日：1998-09-28

Applicant: IBM

Inventor： EMMA PHILIP GEORGE ,  HWANG WEI ,  GATES STEPHEN M

IPC: G11C11/41 ,  G11C11/412 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/11 ,  H01L29/786 ,  H03K19/0944 ,  H03K19/0948 ,  H03K19/20

Abstract: PROBLEM TO BE SOLVED: To obtain a high-density and high-speed merged logic circuit using two semiconductor layers: a thin film and a bulk silicon water layer and to obtain a memory IC chip. SOLUTION: A memory cell uses a three-dimensional(3D) SRAM structure. Two types of 3D logic cells are disclosed. They are of DCVS (DCVSG) architecture in 3D form provided with differential cascade voltage switch(DCVS) architecture in 3D form and pass gate logic. An SRAM memory cell of PMOS transistors Q5 and Q6 with a large logic cell is placed inside a thin-film silicon layer 507. High-speed NMOS transistors Q1-Q4 are placed in a bulk silicon wafer layer 501. A high density is attained in this way.

公开(公告)号：WO2008100324A9

公开(公告)日：2009-05-22

申请号：PCT/US2007071370

申请日：2007-06-15

Applicant: IBM ,  EMMA PHILIP GEORGE ,  KNICKERBOCKER JOHN ULRICH ,  PATEL CHIRAG S

Inventor： EMMA PHILIP GEORGE ,  KNICKERBOCKER JOHN ULRICH ,  PATEL CHIRAG S

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.

Abstract translation: 更具体地说，一种电子计算的方法，更具体地说，一种设计三维芯片中的高速缓存层级的方法，以及由此产生的高速缓存层级，包括在三维实现的高速缓存层级中的位的物理布置，使得在 连接层次结构级别的总线最小化。 以这种方式，电平之间的数据路径主要是通孔本身，这导致非常短的，因此快速和低功率总线。

公开(公告)号：WO2008100324A3

公开(公告)日：2011-01-13

申请号：PCT/US2007071370

申请日：2007-06-15

Applicant: IBM ,  EMMA PHILIP GEORGE ,  KNICKERBOCKER JOHN ULRICH ,  PATEL CHIRAG S

Inventor： EMMA PHILIP GEORGE ,  KNICKERBOCKER JOHN ULRICH ,  PATEL CHIRAG S

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.

Abstract translation: 更具体地说，一种电子计算的方法，更具体地说，一种设计三维芯片中的高速缓存层级的方法，以及由此产生的高速缓存层级，包括在三维实现的高速缓存层级中的位的物理布置，使得在 连接层次结构级别的总线最小化。 以这种方式，电平之间的数据路径主要是通孔本身，这导致非常短的，因此快速和低功率总线。

公开(公告)号：DE3884101T2

公开(公告)日：1994-04-21

申请号：DE3884101

申请日：1988-04-21

Applicant: IBM

Inventor： EMMA PHILIP GEORGE ,  KNIGHT III JOSHUA WILSON ,  POMERENE JAMES HERBERT ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

IPC: G06F9/38 ,  G06F15/16 ,  G06F15/177

公开(公告)号：DE3751474T2

公开(公告)日：1996-03-28

申请号：DE3751474

申请日：1987-02-05

Applicant: IBM

Inventor： EMMA PHILIP GEORGE ,  POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

IPC: G06F9/38

公开(公告)号：DE69715762D1

公开(公告)日：2002-10-31

申请号：DE69715762

申请日：1997-07-22

Applicant: IBM

Inventor： BOZSO FERENC MIKLOS ,  EMMA PHILIP GEORGE

IPC: H01L21/60 ,  G06F1/10 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/02

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

公开(公告)号：DE69030931T2

公开(公告)日：1998-01-15

申请号：DE69030931

申请日：1990-02-06

Applicant: IBM

Inventor： EMMA PHILIP GEORGE ,  KNIGHT JOSHUA WILSON ,  POMERENE JAMES HERBERT ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

IPC: G06F9/38

公开(公告)号：DE69621694T2

公开(公告)日：2003-01-30

申请号：DE69621694

申请日：1996-03-08

Applicant: IBM

Inventor： EMMA PHILIP GEORGE

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/455

Abstract: The invention provides means and methods for extending an instruction-set architecture without impacting the software interface. This circumvents all software compatibility issues, and allows legacy software to benefit from new architectural extensions without recompilation and reassembly. The means employed are a translation engine for translating sequences of old architecture instructions into primary, new architecture instructions, and an extended instruction (EI) cache memory for storing the translations. A processor requesting a sequence of instructions will look first to the EI-cache for a translation, and if translations are unavailable, will look to a conventional cache memory for the sequence, and finally, if still unavailable, will look to a main memory.

公开(公告)号：HK1006242A1

公开(公告)日：1999-02-19

申请号：HK98105470

申请日：1998-06-17

Applicant: IBM

Inventor： BOZSO FERENC MIKLOS ,  EMMA PHILIP GEORGE

IPC: H01L21/60 ,  G06F1/10 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/02 ,  H01L

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.