公开(公告)号：EP1586108A4

公开(公告)日：2009-03-04

申请号：EP02798556

申请日：2002-12-19

Applicant: IBM

Inventor： BREITWISCH MATTHEW ,  NOWAK EDWARD J

IPC: H01L27/11 ,  H01L21/00 ,  H01L21/44 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/11 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/66765 ,  H01L29/785

Abstract: An integrated circuit, such as a SRAM cell (130), including an inverted FinFET transistor (P2) and a FinFET transistor (N3). The inverted FinFET transistor includes a first gate region (108) formed by semiconductor structure (100) on a substrate, a first body region comprised of a semiconductor layer (104), having a first channel region (112) disposed on the first gate region and a source (110) and drain (114) formed on either side of the first channel region. The FinFET transistor (N3) is coupled to the inverted FinFET transistor, and includes a second body region formed by the semiconductor structure (102), having a second channel region (118) and a source (116) and drain (120) formed on either side of the second channel region, and a second gate region (122) comprised of the semiconductor layer, disposed on the second channel region.

公开(公告)号：JP2008066721A

公开(公告)日：2008-03-21

申请号：JP2007222004

申请日：2007-08-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BREITWISCH MATTHEW ,  SCHROTT ALEJANDRO GABRIEL ,  CHAN HON RAMU

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823487 ,  H01L27/088

Abstract: PROBLEM TO BE SOLVED: To provide a vertical type field effect transistor array improved in performance, and a method of manufacturing the same.
SOLUTION: Each vertical part of each semiconductor pillar in a semiconductor pillar array has a line width greater than a separation distance to a neighboring semiconductor pillar. Alternatively, the array may arbitrarily includes a semiconductor pillar having a different line width within the restriction of the line width and the separation distance. A method of manufacturing the array of the semiconductor pillar uses a pillar mask layer created into a minimum dimension using photolithography, at least one of spacer layers of which is increased in an annular manner before it is used as an etching mask.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种提高性能的垂直型场效应晶体管阵列及其制造方法。 解决方案：半导体柱阵列中的每个半导体柱的每个垂直部分具有大于到相邻半导体柱的间隔距离的线宽。 或者，阵列可以任意地包括在线宽和间隔距离的限制内具有不同线宽的半导体柱。 制造半导体柱阵列的方法使用利用光刻法制成最小尺寸的柱掩模层，其中间隔层中的至少一个在用作蚀刻掩模之前以环形方式增加。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008060569A

公开(公告)日：2008-03-13

申请号：JP2007216287

申请日：2007-08-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ALEJANDRO GABRIEL SCHROTT ,  LAM CHUNG H ,  BREITWISCH MATTHEW

IPC: H01L27/105 ,  H01L45/00

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell etc. containing semiconductor features and a phase-change material. SOLUTION: The semiconductor feature defines a groove for dividing the semiconductor feature itself into a first electrode and a second electrode. The phase-change material at least partially fills the groove, and serves to electrically connect the first electrode with the second electrode. In response to a switching signal, added to at least one of the first and second electrodes, at least a part of phase-change material operates so that a low electrical resistance state and a high electrical resistance state are switched. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供包含半导体特征和相变材料的存储单元等。 解决方案：半导体特征限定用于将半导体特征本身分成第一电极和第二电极的凹槽。 相变材料至少部分地填充凹槽，并且用于将第一电极与第二电极电连接。 响应于切换信号，添加到第一和第二电极中的至少一个，至少一部分相变材料操作，从而切换低电阻状态和高电阻状态。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：AU2002364087A1

公开(公告)日：2004-07-22

申请号：AU2002364087

申请日：2002-12-19

Applicant: IBM

Inventor： NOWAK EDWARD J ,  BREITWISCH MATTHEW

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/092 ,  H01L27/11 ,  H01L27/12 ,  H01L21/44 ,  H01L29/00 ,  H01L29/04

公开(公告)号：DE60237724D1

公开(公告)日：2010-10-28

申请号：DE60237724

申请日：2002-12-19

Applicant: IBM

Inventor： BREITWISCH MATTHEW ,  NOWAK EDWARD J

IPC: H01L27/11 ,  H01L21/00 ,  H01L21/44 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

公开(公告)号：AT481736T

公开(公告)日：2010-10-15

申请号：AT02798556

申请日：2002-12-19

Applicant: IBM

Inventor： BREITWISCH MATTHEW ,  NOWAK EDWARD

IPC: H01L27/11 ,  H01L21/00 ,  H01L21/44 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12