公开(公告)号：HK72485A

公开(公告)日：1985-10-04

申请号：HK72485

申请日：1985-09-26

Applicant: IBM

Inventor： BREWER JAMES A ,  EGGEBRECHT LEWIS C ,  KUMMER DAVID A ,  MCHUGH PATRICIA P

IPC: G06F12/02 ,  G11C11/406 ,  G11C7/00 ,  G06F12/16

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.

公开(公告)号：CA1200921A

公开(公告)日：1986-02-18

申请号：CA461008

申请日：1984-08-14

Applicant: IBM

Inventor： BREWER JAMES A ,  KUMMER DAVID A ,  LANGGOOD JOHN K

IPC: H05K1/02

Abstract: There is described a six-layer printed circuit card in which the first, third and sixth layers are signal carrying layers for interconnecting various components forming a personal computer. The second and fifth layers are both ground plane layers and the addition of a second ground plane layer to a printed circuit card reduces the electromagnetic interference emitted from the closely packed components and lines. The final layer of the card is a voltage plane. The components on the printed circuit board include eight input/output (I/O) connectors to which eight other cards controlling various I/O devices can be connected. Seven of the eight I/O connectors are interconnected to a conventional I/O bus. The eight connector is interconnected to some lines of the I/O bus and to some lines of the internal bus throughout the card.

公开(公告)号：GB2103850B

公开(公告)日：1985-03-20

申请号：GB8222691

申请日：1982-08-06

Applicant: IBM

Inventor： BREWER JAMES A ,  EGGEBRECHT LEWIS C ,  MCHUGH PATRICIA P ,  KUMMER DAVID A

IPC: G06F12/02 ,  G11C11/406 ,  G11C7/00 ,  G06F13/00

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.

公开(公告)号：CA1148263A

公开(公告)日：1983-06-14

申请号：CA364206

申请日：1980-11-07

Applicant: IBM

Inventor： BREWER JAMES A ,  LOWY JOHN A

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/14 ,  G06F11/00

Abstract: A high speed readback check of data transferred to a cyclic memory before the data source is lost. The cyclic memory is organized into a number of data blocks, each interleaved with or simultaneously accessible with the other data blocks. Thus, a long data record comprises several data blocks and therefore several cycles of the memory. A readback check of data transferred from a source into the memory is accomplished by writing data into one data block in a first cycle, writing data into another block on the second cycle while reading back the first data block and calculating a check character therefrom, continuing through the writing of the entire record, and reading the last block of written data and calculating the check character, and then comparing the calculated check character with a character calculated from the source data to detect any error before the source of the record is lost.

公开(公告)号：CA1200920A

公开(公告)日：1986-02-18

申请号：CA459093

申请日：1984-07-17

Applicant: IBM

Inventor： BREWER JAMES A ,  LANGGOOD JOHN K ,  MARKHAM HARVEY R

IPC: H05K1/02

Abstract: There is described a six-layer printed circuit card in which the first, third and sixth layers are signal carrying layers for interconnecting various components forming a personal computer. The second and fifth layers are both ground plane layers and the addition of a second ground plane layer to a printed circuit card reduces the electromagnetic interference emitted from the closely packed components and lines. The final layer of the card is a voltage plane. The components on the printed circuit board include eight input/output (I/O) connectors to which eight other cards controlling various I/O devices can be connected. Seven of the eight I/O connectors are interconnected to a conventional I/O bus. The eight connector is interconnected to some lines of the I/O bus and to some lines of the internal bus throughout the card.

公开(公告)号：GB2103850A

公开(公告)日：1983-02-23

申请号：GB8222691

申请日：1982-08-06

Applicant: IBM

Inventor： BREWER JAMES A ,  EGGEBRECHT LEWIS C ,  MCHUGH PATRICIA P ,  KUMMER DAVID A

IPC: G06F12/02 ,  G11C11/406 ,  G11C7/00 ,  G06F13/00

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.