公开(公告)号：HK72485A

公开(公告)日：1985-10-04

申请号：HK72485

申请日：1985-09-26

Applicant: IBM

Inventor： BREWER JAMES A ,  EGGEBRECHT LEWIS C ,  KUMMER DAVID A ,  MCHUGH PATRICIA P

IPC: G06F12/02 ,  G11C11/406 ,  G11C7/00 ,  G06F12/16

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.

公开(公告)号：GB2103850B

公开(公告)日：1985-03-20

申请号：GB8222691

申请日：1982-08-06

Applicant: IBM

Inventor： BREWER JAMES A ,  EGGEBRECHT LEWIS C ,  MCHUGH PATRICIA P ,  KUMMER DAVID A

IPC: G06F12/02 ,  G11C11/406 ,  G11C7/00 ,  G06F13/00

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.

公开(公告)号：GB2103850A

公开(公告)日：1983-02-23

申请号：GB8222691

申请日：1982-08-06

Applicant: IBM

Inventor： BREWER JAMES A ,  EGGEBRECHT LEWIS C ,  MCHUGH PATRICIA P ,  KUMMER DAVID A

IPC: G06F12/02 ,  G11C11/406 ,  G11C7/00 ,  G06F13/00

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a «D-type» latch (24) whose output, is turn, sets the highest priority DMA channel (0) request line (DREQO), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACKO) indicating the cycle is completed.