公开(公告)号：GB2366641B

公开(公告)日：2004-11-10

申请号：GB0109160

申请日：2001-04-12

Applicant: IBM

Inventor： BROBERG ROBERT N ,  BYRN JONATHAN W ,  MCBRIDE CHAD B ,  MCCLANNAHAN GARY P

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/46

Abstract: A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a power-on default address associated with the same interrupt service routine. The method may determine whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Override address registers are accessed via the special purpose registers of the processing unit. A validation bit may be turned on in response to the setting of the override address, with both the default address and the override address being provided as separate inputs to a multiplexing device controlled by the validation bit. The override address is forwarded from the multiplexing device to an instruction fetch unit whenever the validation bit has been set. The result is decreased latency associated with interrupt handling, and increased flexibility in user definition of critical versus non-critical interrupts.

公开(公告)号：GB2366641A

公开(公告)日：2002-03-13

申请号：GB0109160

申请日：2001-04-12

Applicant: IBM

Inventor： BROBERG ROBERT N ,  BYRN JONATHAN W ,  MCBRIDE CHAD B ,  MCCLANNAHAN GARY P

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/46

Abstract: A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a power-on default address associated with the same interrupt service routine. The method may determine whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Override address registers 112 are accessed via the special purpose registers of the processing unit. A validation bit may be turned on in response to the setting of the override address, with both the default address and the override address being provided as separate inputs to a multiplexing device 116 controlled by the validation bit. The override address is forwarded from the multiplexing device to an instruction fetch unit 122 whenever the validation bit has been set. The result is decreased latency associated with interrupt handling, and increased flexibility in user definition of critical versus non-critical interrupts.