ERROR CONTROL SYSTEM
    2.
    发明专利

    公开(公告)号:CA1017867A

    公开(公告)日:1977-09-20

    申请号:CA212863

    申请日:1974-11-01

    Applicant: IBM

    Abstract: In the transmission of variable length frames of digital information separated by one or more flag sequences, a block check is generated and appended to the information bits at the transmitter. The block check is generated by Exclusive OR'ing a predetermined non-zero number to the high order information bits and generating (n-k) check digits according to a cyclic error detecting code. The (n-k) check digits are Exclusive OR'd with an (n-k) bit non-zero number to produce the block check. At the receiver, the first mentioned non-zero number is added to the high order information bits and an (n-k) digit number is generated according to the same cyclic error detecting code used at the transmitter. This number is checked to see if it conforms to a predetermined number indicating error-free transmission. Utilizing the above approach, transmission errors in or near the flag sequence are detected, as well as those which may occur in the information field.

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