Apparatus for detecting circuit malfunctions
    1.
    发明授权
    Apparatus for detecting circuit malfunctions 失效
    检测电路故障的装置

    公开(公告)号:US3562711A

    公开(公告)日:1971-02-09

    申请号:US3562711D

    申请日:1968-07-16

    Applicant: IBM

    CPC classification number: H04L1/0057

    Abstract: A DEVICE FOR DETECTING CIRCUIT MALFUNCTIONS IN CERTAIN LINEAR SWITCHING CIRCUITS OPERATED IN SUCCESSIVE TIME PERIODS WHICH HAS A FIRST CIRCUIT FOR GENERATING A PREDICTED PARITY SIGNAL FOR EACH SUCCESSIVE TIME PERIOD, A PARITY CHECK CIRCUIT FOR GENERATING A SIGNAL INDICATIVE OF ACTUAL PARITY DURING EACH SUCCESSIVE TIME PERIOD, AND A COMPARATOR FOR COMPARING THE SIGNALS REPRESENTING THE PREDICTED PARITY AND THE ACTUAL PARITY DURING EACH SUCCESSIVE TIME PERIOD, THEREBY TO INDICATE ANY CIRCUIT MALFUNCTION DURING EACH SUCH SUCCESSIVE TIME PERIOD.

    CHECKING POLYNOMIAL FOR DETECTING ALL ODD LINE ERRORS WITH SCRAMBLERS

    公开(公告)号:CA984513A

    公开(公告)日:1976-02-24

    申请号:CA170036

    申请日:1973-04-24

    Applicant: IBM

    Abstract: If digital data sequences of length n bits are successively encoded for protection against error by appending to each block of n bits in a sequence of r check bits, the r check bits being calculated from the n bits of the block by iteratively dividing the data stream, by a generator polynomial g(x) prior to each transmission and then by iteratively dividing the data sequence and remainder by a scrambler polynomial S(x), then the apparent error E(x) at the receiver due to channel error e(x), after descrambling (multiplying) by polynomial S(x), is represented by the relation E(x) = S(x) e(x). When scrambling polynomial S(x) is of the form S(x) = 1 + x, then each channel error is replaced by two adjacent errors, hence E(x) = (1 = x) e(x). All single and odd errors are nevertheless detectable in such circumstances by modifying g(x) such that g(x) = (1 + x)m 1 t(x). Furthermore, burst type channel error of length >/= b is detectable, in addition to all single and odd errors, if the scrambler polynomial S(x) assumes the form S(x) = (1 + x)m f(x) and the generator polynomial is modified so that g(x) = (1 + x)m 1 t(x) where f(x) and t(x) are polynomials having an odd number of terms and relatively prime and t(x) is of degree >/= b.

    ERROR CONTROL SYSTEM
    3.
    发明专利

    公开(公告)号:CA1017867A

    公开(公告)日:1977-09-20

    申请号:CA212863

    申请日:1974-11-01

    Applicant: IBM

    Abstract: In the transmission of variable length frames of digital information separated by one or more flag sequences, a block check is generated and appended to the information bits at the transmitter. The block check is generated by Exclusive OR'ing a predetermined non-zero number to the high order information bits and generating (n-k) check digits according to a cyclic error detecting code. The (n-k) check digits are Exclusive OR'd with an (n-k) bit non-zero number to produce the block check. At the receiver, the first mentioned non-zero number is added to the high order information bits and an (n-k) digit number is generated according to the same cyclic error detecting code used at the transmitter. This number is checked to see if it conforms to a predetermined number indicating error-free transmission. Utilizing the above approach, transmission errors in or near the flag sequence are detected, as well as those which may occur in the information field.

Patent Agency Ranking