公开(公告)号：JP2000259412A

公开(公告)日：2000-09-22

申请号：JP2000046359

申请日：2000-02-23

Applicant: IBM

Inventor： KURT ALAN FAIST ,  BRUCE JOSEPH RONSHETTI ,  DAVID JAMES SIPPY

IPC: G06F12/08 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a store transferring method which increases the throughput of an instruction in a processor. SOLUTION: A load/store unit in a microprocessor executes a load instruction and a store instruction in an out-of-order. A tag is allocated to the load and store instructions in a prescribed method and the load and stored instructions are allocated to a load reorder queue and a store reorder queue in order to trace the program sequences of the load and store instructions. When the load instruction is issued to be carried out, it is discriminated whether or not the load instruction tries to load data into a memory position being the same as that of a previously executed store instruction. In that case, data waiting for being stored in a cache by a store instruction are directly transferred to the load instruction.

公开(公告)号：JP2000250810A

公开(公告)日：2000-09-14

申请号：JP2000046172

申请日：2000-02-23

Applicant: IBM

Inventor： MARLIN WAYNE FREDERICK JR ,  BRUCE JOSEPH RONSHETTI ,  DAVID JAMES SIPPY ,  THATCHER LARRY EDWARD

IPC: G06F12/08 ,  G06F9/312 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To improve the execution of a load instruction with a processor by retrieving data from a system memory after the absence of data addressed by a first instruction in a primary cash is discriminated, issuing a second load instruction to these data and returning the data to the first and second load instructions. SOLUTION: The presence/absence of data addressed by a first load instruction in an L1 data cache is discriminated and when the absence of an addressed cache line in the L1 data cache is discriminated, it is discriminated whether an address of the cache line is coincident with the address in the entry of an existent LMQ 218 or not. In the case of coincidence, a request to the cache line is sent to the downstream of a system memory and the data are retrieved from that system memory. A second load instruction is issued to these data by a dispatch unit 271 and these data are returned to both the first and second load instructions.