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公开(公告)号：JPH10320198A
公开(公告)日：1998-12-04
申请号：JP9133098
申请日：1998-04-03
Applicant: IBM
Inventor： FEISTE KURT ALAN , MUHICH JOHN STEPHEN , THATCHER LARRY EDWARD , WHITE STEVEN WAYNE
Abstract: PROBLEM TO BE SOLVED: To transfer stored data to a necessary load instruction without stalling the long instruction until storage completion by transferring store data to the load instruction when a store instruction is already converted, a load address range is included in a store address range, and the store data are usable. SOLUTION: This is a method for transferring data as the result of a store instruction which does not have updated data to the load instruction and a CPU 120 judges whether or not there is a common byte between the address of the load instruction and the address of the store instruction. Further, it is judged whether or not the load instruction is logically behind the store instruction. When there is the common byte between the address of the load instruction and the address of the store instruction and when the load instruction is logically behind the store instruction, the data is transferred to the load instruction.
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公开(公告)号：JP2000339221A
公开(公告)日：2000-12-08
申请号：JP2000135310
申请日：2000-05-09
Applicant: IBM
Inventor： ALBERT CHAN , SILHA EDWARD JOHN , THATCHER LARRY EDWARD , GU WAI-YAN YUN
IPC: G06F12/10
Abstract: PROBLEM TO BE SOLVED: To obtaen a device for invalidating a part of an ERAT entry by providing an address conversion device from a valid address to a real address and a circuit for selectively invalidating the entry of the address conversion device. SOLUTION: Misrequest registers 304, 306 and 308 validate EA of registers (EA) 303, (EA0) 305 and (EA1) 307 with respect to the arbitration register 313 of an LSU conversion device 300. The registers (EA) 303, (EA0) 305 and (EA1) 307 give the valid addresses received by an instruction fetch device 350 and an L/S device 201 to registers 310 to 312 in the LSU device 300. The arbitration register 313 selects one of addresses and sends it to SLB CAM 314. The SLB CAM 314 can be mounted as CAM. In such a mounting form, softwre invalidates an entry at need without directly writing the content of SLB.
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公开(公告)号：JP2000250810A
公开(公告)日：2000-09-14
申请号：JP2000046172
申请日：2000-02-23
Applicant: IBM
Inventor： MARLIN WAYNE FREDERICK JR , BRUCE JOSEPH RONSHETTI , DAVID JAMES SIPPY , THATCHER LARRY EDWARD
Abstract: PROBLEM TO BE SOLVED: To improve the execution of a load instruction with a processor by retrieving data from a system memory after the absence of data addressed by a first instruction in a primary cash is discriminated, issuing a second load instruction to these data and returning the data to the first and second load instructions. SOLUTION: The presence/absence of data addressed by a first load instruction in an L1 data cache is discriminated and when the absence of an addressed cache line in the L1 data cache is discriminated, it is discriminated whether an address of the cache line is coincident with the address in the entry of an existent LMQ 218 or not. In the case of coincidence, a request to the cache line is sent to the downstream of a system memory and the data are retrieved from that system memory. A second load instruction is issued to these data by a dispatch unit 271 and these data are returned to both the first and second load instructions.
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公开(公告)号：DE69815201D1
公开(公告)日：2003-07-10
申请号：DE69815201
申请日：1998-03-06
Applicant: IBM
Inventor： FEISTE KURT ALAN , MUHICH JOHN STEPHEN , THATCHER LARRY EDWARD , WHITE STEVEN WAYNE
Abstract: In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.
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公开(公告)号：MY121300A
公开(公告)日：2006-01-28
申请号：MYPI9800941
申请日：1998-03-04
Applicant: IBM
Inventor： FEISTE KURT ALAN , MUNICH JOHN STEPHEN , THATCHER LARRY EDWARD , WHITE STEVEN WAYNE
Abstract: IN A SUPERSCALAR PROCESSOR (210) IMPLEMENTING OUT-OF-ORDER DISPATCHING AND EXECUTION OF LOAD AND STORE INSTRUCTIONS, WHEN A STORE INSTRUCTION HAS ALREADY BEEN TRANSLATED, THE LOAD ADDRESS RANGE OF A LOAD INSTRUCTION IS CONTAINED WITHIN THE ADDRESS RANGE OF THE STORE INSTRUCTION, AND THE DATA ASSOCIATED WITH THE STORE INSTRUCTION IS AVAILABLE, THEN THE DATA ASSOCIATED WITH THE STORE INSTRUCTION IS FORWARDED TO THE LOAD INSTRUCTION SO THAT THE LOAD INSTRUCTION MAY CONTINUE EXECUTION WITHOUT HAVING TO BE STALLED OR FLUSHED.
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Patent Agency Ranking
公开(公告)号：AT209794T
公开(公告)日：2001-12-15
申请号：AT94306765
申请日：1994-09-15
Applicant: IBM
Inventor： RAY DAVID SCOTT , THATCHER LARRY EDWARD , WARREN HENRY STANLEY JR
IPC: G06F9/38
Abstract: A multiple execution unit processing system is provided wherein each execution unit 17, 19 has an associated instruction buffer 2, 4 and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to be executed in parallel on the execution units.
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公开(公告)号：DE68928015D1
公开(公告)日：1997-06-05
申请号：DE68928015
申请日：1989-12-20
Applicant: IBM
Inventor： NGUYENPHU MYHONG , THATCHER LARRY EDWARD
Abstract: A data processing system including a first processor that performs fixed point arithmetic operations and a second processor that performs floating point arithmetic operations. These two processors are connected by control circuitry that decodes a floating point arithmetic instruction that requires the second processor to perform a specified floating point arithmetic operation. The control circuitry provides information to the first processor to enable the first processor to compute a memory address for accessing the floating point data required by the second processor for performing the specified floating point arithmetic operation. Simultaneously the control circuitry provides the second processor with the information to initiate the execution of the specified floating point arithmetic operation. Also, the data processing system includes the means to access multi-word floating point data on either even or odd memory address boundaries.
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公开(公告)号：AT242509T
公开(公告)日：2003-06-15
申请号：AT98301659
申请日：1998-03-06
Applicant: IBM
Inventor： FEISTE KURT ALAN , MUHICH JOHN STEPHEN , THATCHER LARRY EDWARD , WHITE STEVEN WAYNE
Abstract: In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.
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公开(公告)号：DE69429226T2
公开(公告)日：2002-08-08
申请号：DE69429226
申请日：1994-09-15
Applicant: IBM
Inventor： RAY DAVID SCOTT , THATCHER LARRY EDWARD , WARREN JR
IPC: G06F9/38
Abstract: A multiple execution unit processing system is provided wherein each execution unit 17, 19 has an associated instruction buffer 2, 4 and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to be executed in parallel on the execution units.
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公开(公告)号：ES2165375T3
公开(公告)日：2002-03-16
申请号：ES94306765
申请日：1994-09-15
Applicant: IBM
Inventor： RAY DAVID SCOTT , THATCHER LARRY EDWARD , WARREN HENRY STANLEY JR
IPC: G06F9/38
Abstract: A multiple execution unit processing system is provided wherein each execution unit 17, 19 has an associated instruction buffer 2, 4 and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to be executed in parallel on the execution units.
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