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    2.
    发明专利
    未知

    公开(公告)号：DE1139544B

    公开(公告)日：1962-11-15

    申请号：DEI0016654

    申请日：1959-06-27

    Applicant: IBM DEUTSCHLAND

    Inventor： BRUNSCHWEIGER ALFRED ,  THOMPSON LEONARD HOWARD

    IPC: G06F5/08 ,  G11C19/28

    Abstract: 925,400. Transistor pulse circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 26, 1959 [June 30, 1958], No. 22084/59. Class 40 (6). [Also in Group XIX] A shift register (see Fig. 5) for storing data received on input line 28 as a pulse (representing " 1 ") or no pulse (representing " 0 ") in each bit period, and in which shift pulses for the trigger stages 25, 26, 27 ... of the register are derived from the data pulses, has a pulse generator 38 generating a train of shift pulses following each input pulse, and a gate 36 opened by a mono-stable flip-flop 32 via trigger 35 after 1¢ bit periods have elapsed without receipt of an input pulse. Fig. 6 shows waveforms; the input pulses (a) may each occur anywhere in their respective bit periods and as shown represent the binary number 1111001. Line (b) shows the state of trigger 25, which is set by the " 1 " pulses and reset by the same pulses delayed by unit 44 and passed by " or " gate 45; this resetting shifts data in the register in the normal way. If 1¢ bit periods elapse without an input pulse, 32 (the " recovery " waveform of which is shown at (c)) produces an output pulse 95 (e) which is passed to the shift line 29 (see 89, line (1)) and also switches 35 to open gate 36. The pulse generator 38 includes a ringing circuit tuned to produce a half-cycle in each pulse period and set in operation (line (g)) by each input pulse; this signal differentiated (h) and squared (i) is used to produce shift pulses (j) at the cross-over points of the squared signal. The first of these to be gated via 36 is 81 appearing on the shift line as 90; subsequently (in the absence of a " 1 " bit) they would appear at successive bit intervals. Fig. 7 shows unit 38 in which 52, 53 constitute the ringing circuit referred to above, which is normally undamped but damped and re-phased by conduction of T 1 caused by an input pulse. Differentiation is effected by 57, 60 and squaring by T 3 , T 4 . Circuit 61 produces an output pulse at each excursion of the input signal, a ringing circuit 91, 92 causing a positive pulse from T 4 (which has no effect since T 5 is cut off) to be followed by a negative excursion which instantaneously produces a positive signal out put before the feed-back through 94 is effective. Negative pulses produce a similar output with out ringing, in each case conduction of T 5 damps out ringing after the single output pulse has appeared.

    3.
    发明专利
    未知

    公开(公告)号：DE1424417A1

    公开(公告)日：1968-10-10

    申请号：DEJ0021062

    申请日：1961-12-19

    Applicant: IBM

    Inventor： BRUNSCHWEIGER ALFRED

    IPC: G11B20/10

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