公开(公告)号：JP2007311773A

公开(公告)日：2007-11-29

申请号：JP2007101249

申请日：2007-04-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BICKFORD JEANNE P ,  BUEHLER MARKUS ,  HIBBELER JASON D ,  KOEHL JUERGEN ,  MAYNARD DANIEL N

IPC: H01L21/82 ,  H01L21/66

CPC classification number: G06F17/5077

Abstract: PROBLEM TO BE SOLVED: To provide a method which optimize router settings so as to improve IC yield, and to provide a computer program product. SOLUTION: Yield data in an IC manufacturing line are reviewed so as to identify structure-specific mechanisms that impact the IC yield. Next, with respect to each structure-specific mechanism, a structural identifier including a wire code, a tag and/or unique identifiers is established. With respect to a wire having different width, the structural identifier is established. Subsequently, the weighting factor is established for each structure-specific mechanism in such a way that a higher weighting factor is established with respect to a structure-specific mechanism including a thick wire which is the most proximate to multiple thick wires. The structural identifier and the weighting factor with respect to the spacing produced between single width lines, double width lines, and triple width lines and wires arranged on a large metal land. Then, the router settings are modified based on the structural identifier and the weighting factor so as to minimize systematic defects. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种优化路由器设置以提高IC产量并提供计算机程序产品的方法。 解决方案：审查IC生产线中的产量数据，以便识别影响IC产量的结构特异性机制。 接下来，关于每个结构特定机制，建立包括有线代码，标签和/或唯一标识符的结构标识符。 对于具有不同宽度的导线，建立了结构标识符。 随后，针对每个结构特定机构建立加权因子，使得相对于包括最接近多个粗线的粗线的结构特定机构建立较高的加权因子。 单个宽度线，双宽度线和三条宽度线之间产生的间距的结构标识符和加权因子以及排列在大金属地面上的导线。 然后，基于结构标识符和权重因子修改路由器设置，以便最小化系统缺陷。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：DE112021000317T5

公开(公告)日：2022-10-06

申请号：DE112021000317

申请日：2021-02-23

Applicant: IBM

Inventor： MAURER THILO ,  BUEHLER MARKUS ,  INGIMUNDARSON ARNI ,  STEINMACHER-BUROW BURKHARD

IPC: G06F9/50 ,  G06F9/54

Abstract: Aspekte der Offenbarung betreffen einen Prozessorkern, der eine Ausführungseinheit und eine Auslastungsverhältnis-Steuereinheit enthält. Die Ausführungseinheit ist zum Ausführen eines an die Ausführungseinheit weitergeleiteten Befehls betreibbar. Die Auslastungsverhältnis-Steuereinheit ist betriebsmäßig mit der Ausführungseinheit verbunden. Die Auslastungsverhältnis-Steuereinheit ist zum Steuern eines Auslastungsverhältnisses der Ausführungseinheit betreibbar. Das Auslastungsverhältnis entspricht dem Anteil einer Beobachtungszeit, während derer die Ausführungseinheit Befehle einer Anwendung ausführt. Andere Aspekte der Offenbarung betreffen ein Verfahren zum Erkennen oder Analysieren eines Engpasses in einem Prozessorkern für eine gegebene Anwendung. Das Verfahren enthält ein Steuern eines Auslastungsverhältnisses von mindestens einer Ausführungseinheit des Prozessorkerns und ein Messen der sich ergebenden Anwendungsleistung.

公开(公告)号：GB2469532A

公开(公告)日：2010-10-20

申请号：GB0906740

申请日：2009-04-18

Applicant: IBM

Inventor： BUEHLER MARKUS ,  EHRENREICH SEBASTIAN ,  KOEHL JUERGEN

IPC: G01R31/26 ,  G01R31/28

Abstract: A signal repowering chip 300 comprises an input 303, at least one inverter 302a-i connected in series to the input, and at least one switch 301a-i connected to a test enable signal 304, the switches are configured to allow a signal connected to the input to propagate through the inverters when the test signal is active. An output of the chip may be directly connected to the input. The chip may be configured to be connected to a second chip to form a three-dimensional integrated circuit, and may be configured to repower wiring connections on the second chip. A three-dimensional integrated circuit 100 comprises a first chip 105, the first chip comprising a default voltage layer 101a-b and a plurality of wiring layers 104; and a second chip 103, the second chip comprising at least one repeater, the repeater being connected 106, 107 to the default voltage level, The first chip may be configured to connect to the repeater on the second chip. A method of making a three-dimensional integrated circuit is also disclosed.

公开(公告)号：AT430339T

公开(公告)日：2009-05-15

申请号：AT06760106

申请日：2006-05-18

Applicant: IBM

Inventor： BUEHLER MARKUS ,  COHN JOHN ,  HATHAWAY DAVID ,  HIBBELER JASON ,  KOEHL JUERGEN

IPC: G06F17/50

Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.