THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT
    1.
    发明公开
    THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT 有权
    VERWENDUNG REDUNDANTER ROUTEN ZURVERGRÖSSERUNGVON AUSBEUTE UNDZUVERLÄSSIGKEITEINES VLSI-LAYOUTS

    公开(公告)号:EP1889194A4

    公开(公告)日:2008-10-01

    申请号:EP06760106

    申请日:2006-05-18

    Applicant: IBM

    CPC classification number: G06F17/5077 G06F17/5068

    Abstract: Disclosed is a method and system for inserting redundant paths (40,50) into an integrated circuit. Particularly, the invention provides a method for identifying a single via (30) in a first path (40) connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70). The combination of the first (40) and second paths (50) provides greater redundancy than inserting a redundant via (54) alone. More importantly, such redundant paths (50) provide for redundancy when congestion prevents a redundant via (54) from being inserted adjacent to the single via (30). An embodiment of the method further comprises removing the single via (30) and any redundant wire segments (51), if all of the additional vias (52) used to form the second path can be made redundant.

    Abstract translation: 公开了一种用于将冗余路径(40,50)插入到集成电路中的方法和系统。 特别地,本发明提供了一种用于识别连接两个元件的第一路径(40)中的单个通孔(30)的方法,确定替代路线是否可用于连接两个元件(10,20)(不同于冗余通孔 54)),并且用于将第二路径(50)插入到可用的替代路线(70)中。 第一路径(40)和第二路径(50)的组合提供比单独插入冗余通路(54)更大的冗余。 更重要的是,这种冗余路径(50)在拥塞阻止冗余通路(54)被插入邻近单个通路(30)时提供冗余。 如果可以使用于形成第二路径的所有附加通路(52)变得冗余,则该方法的实施例还包括移除单个通路(30)和任何冗余导线段(51)。

    THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT
    2.
    发明申请
    THE USE OF REDUNDANT ROUTES TO INCREASE THE YIELD AND RELIABILITY OF A VLSI LAYOUT 审中-公开
    使用冗余路由增加VLSI布局的可靠性

    公开(公告)号:WO2006125091A2

    公开(公告)日:2006-11-23

    申请号:PCT/US2006019257

    申请日:2006-05-18

    CPC classification number: G06F17/5077 G06F17/5068

    Abstract: Disclosed is a method and system for inserting redundant paths (40,50) into an integrated circuit. Particularly, the invention provides a method for identifying a single via (30) in a first path (40) connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70). The combination of the first (40) and second paths (50) provides greater redundancy than inserting a redundant via (54) alone. More importantly, such redundant paths (50) provide for redundancy when congestion prevents a redundant via (54) from being inserted adjacent to the single via (30). An embodiment of the method further comprises removing the single via (30) and any redundant wire segments (51), if all of the additional vias (52) used to form the second path can be made redundant.

    Abstract translation: 公开了一种用于将冗余路径(40,50)插入到集成电路中的方法和系统。 特别地,本发明提供一种用于在连接两个元件的第一路径(40)中识别单个通孔(30)的方法,确定替代路径是否可用于连接两个元件(10,20)(除了冗余通孔 54)),并且用于将第二路径(50)插入到可用替代路线(70)中。 第一(40)和第二路径(50)的组合提供比单独插入冗余通路(54)更大的冗余。 更重要的是,当拥塞阻止冗余通路(54)相邻于单通道(30)插入时,这种冗余路径(50)提供冗余。 如果用于形成第二路径的所有附加通孔(52)可以是冗余的,则该方法的实施例还包括移除单个通孔(30)和任何冗余线段(51)。

    3.
    发明专利
    未知

    公开(公告)号:DE602006006567D1

    公开(公告)日:2009-06-10

    申请号:DE602006006567

    申请日:2006-05-18

    Applicant: IBM

    Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.

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