公开(公告)号：EP1920262A4

公开(公告)日：2010-11-10

申请号：EP06789035

申请日：2006-08-01

Applicant: IBM

Inventor： BEATTY HARRY J III ,  HATHAWAY DAVID J ,  SUESS ALEXANDER J

IPC: G01R31/317

CPC classification number: G01R31/31725

公开(公告)号：EP1889194A4

公开(公告)日：2008-10-01

申请号：EP06760106

申请日：2006-05-18

Applicant: IBM

Inventor： BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068

Abstract: Disclosed is a method and system for inserting redundant paths (40,50) into an integrated circuit. Particularly, the invention provides a method for identifying a single via (30) in a first path (40) connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70). The combination of the first (40) and second paths (50) provides greater redundancy than inserting a redundant via (54) alone. More importantly, such redundant paths (50) provide for redundancy when congestion prevents a redundant via (54) from being inserted adjacent to the single via (30). An embodiment of the method further comprises removing the single via (30) and any redundant wire segments (51), if all of the additional vias (52) used to form the second path can be made redundant.

Abstract translation: 公开了一种用于将冗余路径（40,50）插入到集成电路中的方法和系统。 特别地，本发明提供了一种用于识别连接两个元件的第一路径（40）中的单个通孔（30）的方法，确定替代路线是否可用于连接两个元件（10,20）（不同于冗余通孔 54）），并且用于将第二路径（50）插入到可用的替代路线（70）中。 第一路径（40）和第二路径（50）的组合提供比单独插入冗余通路（54）更大的冗余。 更重要的是，这种冗余路径（50）在拥塞阻止冗余通路（54）被插入邻近单个通路（30）时提供冗余。 如果可以使用于形成第二路径的所有附加通路（52）变得冗余，则该方法的实施例还包括移除单个通路（30）和任何冗余导线段（51）。

公开(公告)号：JP2002215706A

公开(公告)日：2002-08-02

申请号：JP2001338435

申请日：2001-11-02

Applicant: IBM

Inventor： COHN JOHN M ,  DEAN ALVAR A ,  HATHAWAY DAVID J ,  LACKEY DAVID E ,  LEPSIC THOMAS M ,  LICHTENSTEIGER SUSAN K ,  TETREAULT SCOTT A ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a logical and physical constitution for a voltage island. SOLUTION: In design of a semiconductor chip, it is parted by the unit of bin, which means plural ranges in the design. Design of one semiconductor chip can thus be sliced to various ranges, and these ranges can be allotted to various voltage levels. Each bin can be regarded as one voltage island. Circuits in the design can be added to various bins, or eliminated from the various bins. Circuit speed and power can be increased or reduced by this. When the circuit is disposed in the bin to which a high voltage is allotted, speed and power are increased. When the circuit is disposed in the bin having a low voltage, speed and power are reduced. The size and position of the bin can also be changed. By repeating these steps, the optimum power consumption can be achieved while satisfying other standards such as constraint related to speed.

公开(公告)号：WO2006125091A2

公开(公告)日：2006-11-23

申请号：PCT/US2006019257

申请日：2006-05-18

Applicant: IBM ,  BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

Inventor： BUEHLER MARKUS T ,  COHN JOHN M ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068

Abstract: Disclosed is a method and system for inserting redundant paths (40,50) into an integrated circuit. Particularly, the invention provides a method for identifying a single via (30) in a first path (40) connecting two elements, determining if an alternate route is available for connecting the two elements (10,20) (other than a redundant via (54)), and for inserting a second path (50)into the available alternate route (70). The combination of the first (40) and second paths (50) provides greater redundancy than inserting a redundant via (54) alone. More importantly, such redundant paths (50) provide for redundancy when congestion prevents a redundant via (54) from being inserted adjacent to the single via (30). An embodiment of the method further comprises removing the single via (30) and any redundant wire segments (51), if all of the additional vias (52) used to form the second path can be made redundant.

Abstract translation: 公开了一种用于将冗余路径（40,50）插入到集成电路中的方法和系统。 特别地，本发明提供一种用于在连接两个元件的第一路径（40）中识别单个通孔（30）的方法，确定替代路径是否可用于连接两个元件（10,20）（除了冗余通孔 54）），并且用于将第二路径（50）插入到可用替代路线（70）中。 第一（40）和第二路径（50）的组合提供比单独插入冗余通路（54）更大的冗余。 更重要的是，当拥塞阻止冗余通路（54）相邻于单通道（30）插入时，这种冗余路径（50）提供冗余。 如果用于形成第二路径的所有附加通孔（52）可以是冗余的，则该方法的实施例还包括移除单个通孔（30）和任何冗余线段（51）。

公开(公告)号：JP2002328962A

公开(公告)日：2002-11-15

申请号：JP2002031625

申请日：2002-02-08

Applicant: IBM

Inventor： COHN JOHN M ,  DEAN ALVAR A ,  AMIR H FARRAHI ,  HATHAWAY DAVID J ,  THOMAS M RESHIKKU ,  JAGANATHAN NAGASHIMAAN ,  SCOTT A TETORAATO ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure which reduces power consumption on a microelectronic circuit. SOLUTION: This method distinguishes at least one wiring pair including the first wiring and the second wiring. The second wiring is already tristated or tristatable. The wiring pair has same directional probability over the prescribed or the user selected minimum same directional switching availability for one clock cycle. Or, the wiring pair has opposite directional probability over the prescribed or the user selected minimum opposite directional switching availability for one clock cycle. The first and the second wiring satisfies at least one mathematical relation, and this mathematical relation includes distance between the first and the second wiring, and common run length of the first and the second wiring.

公开(公告)号：JP2002230066A

公开(公告)日：2002-08-16

申请号：JP2001369057

申请日：2001-12-03

Applicant: IBM

Inventor： COHN JOHN M ,  DEAN ALVAR A ,  HATHAWAY DAVID J ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  G06F1/32

Abstract: PROBLEM TO BE SOLVED: To provide a logic system designing method for reducing leak by forcing the sate of a logical gate based on probabilistic analysis. SOLUTION: This method for reducing the leak power of a logical network comprises a step for identifying the 'sleep state' of each net by using observability don't care information, a step for determing at least one net in which expected power consumption is reduced by forcing a net to a specific value during at least a part of the sleep state based on probabilistic analysis, and a step for forcing the determined net to the determined value during the determined part of the sleep state.

公开(公告)号：CA1287174C

公开(公告)日：1991-07-30

申请号：CA580777

申请日：1988-10-20

Applicant: IBM

Inventor： HATHAWAY DAVID J

IPC: G06F17/50 ,  G06F15/60

Abstract: An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.

公开(公告)号：DE602006006567D1

公开(公告)日：2009-06-10

申请号：DE602006006567

申请日：2006-05-18

Applicant: IBM

Inventor： BUEHLER MARKUS T ,  COHN JOHN M OLD JONES ,  HATHAWAY DAVID J ,  HIBBELER JASON D ,  KOEHL JUERGEN

IPC: G06F17/50

Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.