公开(公告)号：JP2004326748A

公开(公告)日：2004-11-18

申请号：JP2004105227

申请日：2004-03-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BURKY WILLIAM E ,  KALLA RONALD N ,  BARARAMU SHINHAROI ,  WARD III JOHN W

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F12/10

CPC classification number: G06F9/3851 ,  G06F9/3861 ,  G06F9/3867

Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for detecting and dealing with function stop of exception condition due to use of resource.
SOLUTION: The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions of a selected thread are flushed. A detected exception condition is resolved by issuing a following instruction. Until the exception condition is resolved, resources for allowing the second thread to dispatch are not be released which can prevent dispatch of the first thread for resolving the exception condition. A flush of the first thread does not resolve the function stop rather a dispatch flush of the second thread is issued. If a second thread instruction has long latency resource requirements that prevent the first thread from dispatching to resolve the exception, a hold is issued controlling when the second thread instruction is refetched.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004326738A

公开(公告)日：2004-11-18

申请号：JP2004064719

申请日：2004-03-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BURKY WILLIAM E ,  KLIM PETER J ,  LE HUNG Q

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/30181 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To dispatch and issue a new instruction group as quickly as possible in an SMT (simultaneous multi-thread) system.
SOLUTION: The SMT system 119 has a dynamically shared GCT (a group completion table) 301. Performance of the SMT is improved by configuring the GCT to allow the instruction group from each thread to complete simultaneously. The GCT has a read port 304, 354 for each thread corresponding to the completion table instruction/address array for simultaneous updating on completion. The forward link array also has a read port for each thread to find the next instruction group for each thread upon completion. The backward link array has a backward link write port for each thread in order to update the backward links for each thread simultaneously. The GCT has independent pointer management means 336, 334 for each thread.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2010146550A

公开(公告)日：2010-07-01

申请号：JP2009243223

申请日：2009-10-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CAPPS LOUIS ,  SHAPIRO MICHAEL ,  BELL JR ROB ,  COOK THOMAS ,  BURKY WILLIAM E

IPC: G06F9/50 ,  G06F9/38

CPC classification number: G06F9/5061 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3887

Abstract: PROBLEM TO BE SOLVED: To automatically, dynamically and repeatedly reconfigure a processor for optimal performance based on characteristics of currently executing software.
SOLUTION: A plurality of cores of the processor are dynamically combined into larger cores that run complex operations with improved efficiency. A plurality of cores of an integrated circuit are selectively combined into functional groups by high-speed communication paths between the cores of a functional group so that a first core manages secondary cores that help perform a workload. The first core takes over secondary cores to create a combination of cores that functions as a single core so that complex functions are executed on the combination of cores in fewer cycles than would be used for a single core. Complex workloads are effectively managed using simple cores to provide efficient processing with a simplified processor design.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：基于当前执行的软件的特性，自动，动态地和重复地重新配置处理器以获得最佳性能。 解决方案：将处理器的多个核心动态组合成更大的核心，以更高的效率运行复杂的操作。 集成电路的多个核心通过功能组的核心之间的高速通信路径选择性地组合成功能组，使得第一核心管理辅助执行工作负载的次级核心。 第一个核心是接管二级核心，以创建一个核心的组合，这些核心可以作为一个核心，以便在核心组合中执行复杂的功能，而这些核心的周期要比单个核心所用的周期少。 使用简单的内核有效地管理复杂的工作负载，以便通过简化的处理器设计提供高效的处理。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：WO2009094674A3

公开(公告)日：2010-01-21

申请号：PCT/US2009035251

申请日：2009-02-26

Applicant: IBM ,  BLANER BARTHOLOMEW ,  BROWN MARY D ,  BURKY WILLIAM E ,  VENTON TODD A

Inventor： BLANER BARTHOLOMEW ,  BROWN MARY D ,  BURKY WILLIAM E ,  VENTON TODD A

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/10 ,  G06F1/3237 ,  Y02D10/128

Abstract: A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register (112) in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers (116) in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs (202) used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register (112) in the second pipeline stage.

Abstract translation: 一种用于在多级流水线设计中实现数字逻辑电路的推测时钟门控的方法包括在第一流水线级n中产生输入到第二流水线级n + 1中的第一寄存器（112）的有效控制信号， 指示何时由第二流水线级n + 1执行操作的有效控制信号; 以及在所述第一流水线级中产生用于在第二流水线级中向多个附加寄存器（116）门控时钟信号的推测有效控制信号，其中所述推测有效控制信号仅使用 用于产生有效控制信号的控制输入（202）的总数，并且其中在第二流水线级中将时钟信号直接发送到第一流水线级的第一寄存器（112）。

公开(公告)号：CA2289402A1

公开(公告)日：2000-05-30

申请号：CA2289402

申请日：1999-11-12

Applicant: IBM

Inventor： ARROYO RONALD XAVIER ,  JOYNER JODY B ,  BURKY WILLIAM E

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16

Abstract: A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.

公开(公告)号：CA2289402C

公开(公告)日：2009-06-02

申请号：CA2289402

申请日：1999-11-12

Applicant: IBM

Inventor： ARROYO RONALD XAVIER ,  BURKY WILLIAM E ,  JOYNER JODY B

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16

Abstract: A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.