-
公开(公告)号：CA2289402A1
公开(公告)日：2000-05-30
申请号：CA2289402
申请日：1999-11-12
Applicant: IBM
Inventor： ARROYO RONALD XAVIER , JOYNER JODY B , BURKY WILLIAM E
Abstract: A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.
-
公开(公告)号：CA2289402C
公开(公告)日：2009-06-02
申请号：CA2289402
申请日：1999-11-12
Applicant: IBM
Inventor： ARROYO RONALD XAVIER , BURKY WILLIAM E , JOYNER JODY B
Abstract: A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.
-
Search Results
2
records
(took 0.016 seconds)
