公开(公告)号：GB2511446A

公开(公告)日：2014-09-03

申请号：GB201408707

申请日：2012-11-20

Applicant: IBM

Inventor： CABEZAS VICTORIA CAPARROS ,  JONGERIUS RIK ,  SCHMATZ MARTIN LEO ,  STANLEY-MARBELL PHILLIP

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/14 ,  G06F13/16

Abstract: It is proposed a method implemented by a logic of a computer memory control unit, wherein the control unit comprises at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N ≥ 2 non-cooperative processors via the second interfaces, and the logic is operatively coupled to said first and second interfaces. The method comprises receiving (S10), via said second interfaces, a request to access data of the main physical memory from a first processor of the set, evaluating (S20) if a second processor has previously accessed the data requested by the first processor, and deferring (S30) the request from the first processor when the evaluation (S20) is positive, or, granting (S40) the request from the first processor when the evaluation is negative.