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公开(公告)号：WO02057924A3
公开(公告)日：2003-06-26
申请号：PCT/GB0200123
申请日：2002-01-15
Inventor： CRANFORD HAYDEN CLAVIE , NORMAN VERNON ROBERTS , SCHMATZ MARTIN LEO
CPC classification number: H03L7/08 , H03L7/095 , H03L7/0995 , H03L7/10 , H04L7/0337 , H04L2027/0067
Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL) , a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
Abstract translation: 描述了统一的单向串行链路，用于通过诸如芯片到芯片或卡到卡互连的有线介质提供数据。 它由一个传输部分和一个接收部分组成，它们被成对地运行以允许串行数据通信。 串行链路作为VLSI ASIC模块的一部分实现，并从主机模块中获得其功率，数据和时钟要求。 逻辑发送器部分包含锁相环（PLL），双位数据寄存器，有限脉冲响应（FIR）滤波器和发送数据寄存器。 锁相环包括数字粗回路和模拟精密回路。 数字接收机部分包含PLL，FIR相位旋转器，相位旋转器控制状态机和时钟缓冲器。 发射机和接收机各自优选地利用伪随机比特流（PRBS）生成器和检查器。
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公开(公告)号：WO2013088283A3
公开(公告)日：2013-11-07
申请号：PCT/IB2012056562
申请日：2012-11-20
Applicant: IBM , IBM RES GMBH
CPC classification number: G06F12/0835 , G06F12/0804 , G06F12/14 , G06F13/1663
Abstract: It is proposed a method implemented by a logic of a computer memory control unit, wherein the control unit comprises at least one first interface and second interfaces and is adapted to be connected with a main physical memory via the first interface, and a set of N >= 2 non-cooperative processors via the second interfaces, and the logic is operatively coupled to said first and second interfaces. The method comprises receiving (S10), via said second interfaces, a request to access data of the main physical memory from a first processor of the set, evaluating (S20) if a second processor has previously accessed the data requested by the first processor, and deferring (S30) the request from the first processor when the evaluation (S20) is positive, or, granting (S40) the request from the first processor when the evaluation is negative.
Abstract translation: 提出了一种由计算机存储器控制单元的逻辑实现的方法，其中控制单元包括至少一个第一接口和第二接口，并且适于经由第一接口与主物理存储器连接，并且一组N > = 2个非协作处理器，并且逻辑可操作地耦合到所述第一和第二接口。 所述方法包括：从所述第二接口接收（S10）从所述组的第一处理器访问所述主物理存储器的数据的请求，如果第二处理器先前已经访问了由所述第一处理器请求的数据，则评估（S20） 以及当评估（S20）为肯定时推迟（S30）来自第一处理器的请求，或者当评估为否定时，授予（S40）来自第一处理器的请求。
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公开(公告)号：WO02058355A3
公开(公告)日：2003-02-20
申请号：PCT/GB0200128
申请日：2002-01-15
Inventor： CRANFORD HAYDEN CLAVIE , NORMAN VERNON ROBERTS , SCHMATZ MARTIN LEO
CPC classification number: G06F13/423
Abstract: A global architecture for a serial link connection between two cards which must transmit data across wired media is provided. The architecture comprises a transmitter portion and a receiver portion. The transmitter portion includes a structure and circuitry to take digital bits from a first bit register, such as for example, an eight-bit register or a ten-bit register, and convert these bits into serial analog transmission to the receiver portion. The receiver portion includes a structure and circuitry to sample the analog transmission of the original digital bits and reconvert the analog serial signal of the digital bits corresponding to the original digital bits and store them in a second bit register comparable to the data stored in the original register from which they were selected.
Abstract translation: 提供了必须通过有线媒体传输数据的两张卡之间的串行链路连接的全球架构。 该架构包括发射机部分和接收机部分。 发送器部分包括从第一位寄存器（例如，八位寄存器或十位寄存器）获取数字位的结构和电路，并将这些位转换成到接收器部分的串行模拟传输。 接收器部分包括对原始数字位的模拟传输进行采样并重新对应于原始数字位的数字位的模拟串行信号的结构和电路，并将其存储在与存储在原始数据中的数据相当的第二位寄存器中 他们被选中的注册表。
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公开(公告)号：DE112018001156T5
公开(公告)日：2019-12-05
申请号：DE112018001156
申请日：2018-04-09
Applicant: IBM
Inventor： SCHMATZ MARTIN LEO
IPC: H04L12/24
Abstract: Es wird ein Verfahren zum Vernetzen von Knoten in einer Rechenzentrum-Netzwerkstruktur bereitgestellt, beinhaltend das Verbinden von mindestens zehn Grundeinheiten, die jeweils Knoten aufweisen, die mit Southbound-Verbindungen einer Multi-Host-NIC-Steuereinheit verbunden sind, die nach oben (northbound) eine höhere Gesamtbandbreite als nach unten (southbound) aufweist, wobei die Steuereinheiten als Dragonfly-Vermittlungseinheiten konfiguriert sind; das Verbinden der zehn Grundeinheiten mit deren jeweiligen Steuereinheiten in Form eines abgewandelten Petersen-Graphen als gruppeninternes Netzwerk zum Bilden einer Supereinheit, die drei Gruppen beinhaltet, wobei jede Steuereinheit drei Northbound-Verbindungen für eine direkte Verbindung zu drei anderen Grundeinheiten der Supereinheit verwendet, und wobei zwei Grundeinheiten jeder Gruppe über eine jeweilige vierte Northbound-Verbindung mit einer der anderen Gruppen verbunden ist, und wobei eine verbleibende Grundeinheit, die kein Teil einer der Gruppen ist, zur Verwendung von drei Northbound-Verbindungen für eine direkte Verbindung mit einer Grundeinheit in jeder Gruppe eingerichtet ist.
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公开(公告)号：DE112016005363T5
公开(公告)日：2018-08-16
申请号：DE112016005363
申请日：2016-12-19
Applicant: IBM
Inventor： ABEL FRANCOIS , CLAUBERG ROLF , DOERING ANDREAS CHRISTIAN , SAGMEISTER PATRICIA , SCHMATZ MARTIN LEO
IPC: G06F3/00
Abstract: Ein von einem Computer umgesetztes Verfahren enthält ein Verwalten von Funktionsaufrufen zwischen einer Mehrzahl von Knoten und einem übergeordneten Knoten eines Rack-Systems mit einem verteilten Betriebssystem (OS). Das Betriebssystem enthält eine Mehrzahl von Funktionen, die in mindestens eine erste Klasse und eine zweite Klasse unterteilt sind, und jeder der Mehrzahl von Knoten schließt Funktionen in der zweiten Klasse aus. Das Verwalten der Funktionsaufrufe enthält ein Erfassen eines Aufrufs an eine erste Funktion auf einem ersten Knoten der Mehrzahl von Knoten. Es wird bestimmt, dass die erste Funktion zu der zweiten Klasse von Funktionen gehört und auf dem ersten Knoten nicht zur Verfügung steht. Der Aufruf an die erste Funktion wird zu dem übergeordneten Knoten weitergeleitet in Reaktion auf das Bestimmen, dass die erste Funktion zu der zweiten Klasse gehört, wobei der übergeordnete Knoten Code für die Funktionen in der zweiten Klasse enthält.
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Patent Agency Ranking
公开(公告)号：DE60227048D1
公开(公告)日：2008-07-24
申请号：DE60227048
申请日：2002-01-15
Applicant: IBM
Inventor： CRANFORD HAYDEN CLAVIE , NORMAN VERNON ROBERTS , SCHMATZ MARTIN LEO
Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
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公开(公告)号：AT330362T
公开(公告)日：2006-07-15
申请号：AT02716131
申请日：2002-01-15
Applicant: IBM
Inventor： CRANFORD HAYDEN CLAVIE , GARVIN STACY JEAN , NORMAN VERNON ROBERTS , OWCZARSKI PAUL ALAN , SCHMATZ MARTIN LEO , STEVENS JOSEPH MARSH
Abstract: The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.
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公开(公告)号：AU2002219371A1
公开(公告)日：2002-07-30
申请号：AU2002219371
申请日：2002-01-15
Applicant: IBM
Inventor： NORMAN VERNON ROBERTS , CRANFORD HAYDEN CLAVIE , SCHMATZ MARTIN LEO
Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.
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公开(公告)号：GB2526565A
公开(公告)日：2015-12-02
申请号：GB201409416
申请日：2014-05-28
Applicant: IBM
Inventor： DOERING CHRISTIAN , HELLER RALPH , LUIJTEN RONALD PETER , SCHMATZ MARTIN LEO
Abstract: A compact assembly 10 of printed circuit boards (PCBs) comprises first and second PCBs 21, 22 maintained parallel and facing each other, each having first and second opposing sides. The second PCB 22 has a first set of side connectors C1 on its first side 221 and a second set of side connectors C2 on its second side 222, each configured for both electrical power supply to and signal communication to and/or from the second PCB. The second PCB is electrically and mechanically connected to the the first PCB via an elastomeric connector 31 located between the first side connectors of the second PCB and the second side 212 of the first PCB and is electrically connected to the first PCB via the second side connectors and a flexible electrical connector 40 which may be a flat flexible cable connecting the second set of side connectors and the first PCB. There may be a second elastomeric connector 32 located between the second set of side connectors C2 and the flexible connector 40. A U shape clamp connector 50 may fasten the assembly by mechanical pressure at a lateral edge of the PCBs. There may be multiple double-sided second PCBs such as mSATA PCBs carrying flash memories 61, 62 located on either side of a first storage module PCB (see Fig. 2).
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公开(公告)号：GB2519534A
公开(公告)日：2015-04-29
申请号：GB201318712
申请日：2013-10-23
Applicant: IBM
Inventor： SCHMATZ MARTIN LEO , TRIVEDI ANIMESH KUMAR , METZLER BERNARD , STUEDI PATRICK
IPC: G06F12/10 , G06F12/06 , G06F12/08 , G06F12/0866 , G06F12/0868 , G06F12/1081 , G06F15/173
Abstract: The application discloses a persistent caching system which includes a storage system having at least one caching server for storing data, and clients for accessing the data through a network. The caching server is configured to store the data in a number of virtual memory blocks, each of the virtual memory blocks referring to an associated memory-mapped file in a file system of the caching server. Further, the caching server is configured to export addresses of the virtual memory blocks to each of the clients. Each of the clients is configured to access at least some of the virtual memory blocks through Remote Direct Memory Access (RDMA) using at least some of the exported addresses. The caching server is further configured to page one or more virtual memory blocks being accessed by one or more clients through RDMA to and/or from the memory-mapped files associated with the accessed virtual memory blocks.
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