公开(公告)号：DE3371127D1

公开(公告)日：1987-05-27

申请号：DE3371127

申请日：1983-08-31

Applicant: IBM

Inventor： KIDA MASUYOSHI ,  TUNG MIN-HSIUNG GEORGE ,  USHIRODA TATSUYUKI ,  CANNISTRA ANTHONY T

IPC: G06K7/00 ,  G06K7/015

公开(公告)号：FR2276737A1

公开(公告)日：1976-01-23

申请号：FR7515549

申请日：1975-05-09

Applicant: IBM

Inventor： CANNISTRA ANTHONY T ,  PETROSKY JOSEPH A JR

IPC: H03K19/017 ,  H03K19/0948 ,  H03K19/08

Abstract: 1506234 Transistor logic circuits INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [27 June 1974 (2)] 21851/75 Heading H3T A logic circuit comprises a plurality of input FETs T40... T46 of a first channel type connected in parallel between an output terminal and a reference potential terminal, a further FET T48 of the opposite channel type connected between the output terminal and a second potential terminal +V and a series arrangement of further FETs T41... T47 connected as shown and arranged to turn on the FET T48 so as to accelerate changes in the output. The circuit shown provides an NOR function. In Fig. 8 (not shown) R3 is omitted and four P-channel FETs are connected between the respective interconnections of FETs T41...T47 and potential terminal +V so as to provide a speed-up function.

公开(公告)号：CA1023814A

公开(公告)日：1978-01-03

申请号：CA225984

申请日：1975-04-29

Applicant: IBM

Inventor： CANNISTRA ANTHONY T ,  PETROSKY JOSEPH A JR

IPC: H03K19/0948 ,  H03K19/08 ,  H03K19/094

公开(公告)号：DE2525690A1

公开(公告)日：1976-01-08

申请号：DE2525690

申请日：1975-06-10

Applicant: IBM

Inventor： CANNISTRA ANTHONY T ,  PETROSKY JUN JOSEPH A

IPC: H03K19/017 ,  H03K19/0948 ,  H03K19/08

Abstract: 1506234 Transistor logic circuits INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [27 June 1974 (2)] 21851/75 Heading H3T A logic circuit comprises a plurality of input FETs T40... T46 of a first channel type connected in parallel between an output terminal and a reference potential terminal, a further FET T48 of the opposite channel type connected between the output terminal and a second potential terminal +V and a series arrangement of further FETs T41... T47 connected as shown and arranged to turn on the FET T48 so as to accelerate changes in the output. The circuit shown provides an NOR function. In Fig. 8 (not shown) R3 is omitted and four P-channel FETs are connected between the respective interconnections of FETs T41...T47 and potential terminal +V so as to provide a speed-up function.