公开(公告)号：CA1023814A

公开(公告)日：1978-01-03

申请号：CA225984

申请日：1975-04-29

Applicant: IBM

Inventor： CANNISTRA ANTHONY T ,  PETROSKY JOSEPH A JR

IPC: H03K19/0948 ,  H03K19/08 ,  H03K19/094

公开(公告)号：FR2305058A1

公开(公告)日：1976-10-15

申请号：FR7602503

申请日：1976-01-27

Applicant: IBM

Inventor： FREEMAN LEO B JR ,  INCERTO ROBERT J ,  PETROSKY JOSEPH A JR

IPC: H03F3/343 ,  H03F3/34 ,  H03F3/45 ,  H03K17/687 ,  H03K19/0175

Abstract: A dual channel high gain differential amplifier utilizing enhancement depletion MOS field effect transistors which exhibits high common mode rejection and fast switching characteristics.

公开(公告)号：FR2313819A1

公开(公告)日：1976-12-31

申请号：FR7613464

申请日：1976-04-29

Applicant: IBM

Inventor： FREEMAN LEO B ,  INCERTO ROBERT J ,  PETROSKY JOSEPH A JR

IPC: G11C11/412 ,  H01L21/8236 ,  H01L27/088 ,  H01L29/78 ,  H03K3/356 ,  H03K17/00 ,  H03K17/041 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/08 ,  G11C11/40

Abstract: A circuit comprising the parallel connection of an enhancement-and a depletion-type FET which exhibits reduced power and improved performance for both logic as well as memory circuits.

公开(公告)号：CA1058325A

公开(公告)日：1979-07-10

申请号：CA254113

申请日：1976-06-04

Applicant: IBM

Inventor： FREEMAN LEO B ,  INCERTO ROBERT J ,  PETROSKY JOSEPH A JR

IPC: G11C11/412 ,  H01L21/8236 ,  H01L27/088 ,  H01L29/78 ,  H03K3/356 ,  H03K17/00 ,  H03K17/041 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/08 ,  G11C11/40

Abstract: ENHANCEMENT-AND DEPLETION-TYPE FIELD EFFECT TRANSISTORS CONNECTED IN PARALLEL A circuit comprising the parallel connection of an enhancement-and a depletion-type FET which exhibits reduced power and improved performance for both logic as well as memory circuits. Cross-coupled enhancement-type field effect transistors and first and second sets of field effect transistors connect the internal switching nodes of the cross-coupled transistors to bit-sense lines. The first and second sets of field effect transistors each comprise a depletion-type field effect transistor and an enhancementtype field effect transistor connected in parallel.

公开(公告)号：FR2276737A1

公开(公告)日：1976-01-23

申请号：FR7515549

申请日：1975-05-09

Applicant: IBM

Inventor： CANNISTRA ANTHONY T ,  PETROSKY JOSEPH A JR

IPC: H03K19/017 ,  H03K19/0948 ,  H03K19/08

Abstract: 1506234 Transistor logic circuits INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [27 June 1974 (2)] 21851/75 Heading H3T A logic circuit comprises a plurality of input FETs T40... T46 of a first channel type connected in parallel between an output terminal and a reference potential terminal, a further FET T48 of the opposite channel type connected between the output terminal and a second potential terminal +V and a series arrangement of further FETs T41... T47 connected as shown and arranged to turn on the FET T48 so as to accelerate changes in the output. The circuit shown provides an NOR function. In Fig. 8 (not shown) R3 is omitted and four P-channel FETs are connected between the respective interconnections of FETs T41...T47 and potential terminal +V so as to provide a speed-up function.