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    2.
    发明专利
    未知

    公开(公告)号：FR2309089A1

    公开(公告)日：1976-11-19

    申请号：FR7514020

    申请日：1975-04-25

    Applicant: IBM FRANCE

    Inventor： CARON FRANCOIS ,  DESBLACHE ANDRE ,  GODARD DOMINIQUE ,  MADDENS FRANCIS

    IPC: H04L25/40 ,  H03K5/00 ,  H03L7/00 ,  H03L7/06 ,  H03L7/08 ,  H04L7/027 ,  H04L7/033 ,  H04L7/04 ,  H04L27/06 ,  H04L7/02

    Abstract: 1492165 APC systems INTERNATIONAL BUSINESS MACHINES CORP 24 March 1976 [25 April 1975] 11806/76 Heading H3A A synchronization arrangement for adjusting the phase of clock signals defining the sampling instants of a received digital data i.e. a modulated carrier fc comprises a controlled oscillator 14 for producing the clock signals and a control circuit 15 including (see Fig. 3) a first filter 16 for extracting from the received signal an upper sideband component of phase # 1 and frequency fc + 1/2T, where 1/T is the data rate, a second filter 18 for extracting a lower sideband component of phase # 2 and frequency fc-1/2T, a circuit 17, 19, 20 for producing from the two components a signal representing # 2 -# 1 for controlling the clock signals. The oscillator may be a quartz oscillator providing a squared output and applied to a set of dividers whose division ratio is varied by the error control signal produced by circuit 15 so that the clock sampling instants at 4 correspond to specific instants in the received data and associated with particular sideband information. The sampled data may be applied via an A/D converter 6 or direct to the control circuit 15. The filters 16, 18 may be narrow-band recursive digital filters (Figs. 4, 8, not shown). The filtered outputs are multiplied at 17 and low pass filtered at 19 and applied via a circuit 20 to obtain a sinusoidal function of the phase error. The need for a low-pass filter may be obviated by employing filters 16, 18 which produce quadrature outputs (Figs. 6, 9, not shown). A second order feed-back loop (Fig. 7, not shown) provides better frequency drift correction. For synchronizing the receiver and transmitter clocks, an initialization sequence may be transmitted before the data and the receiver may be modified (Fig. 9, not shown) to selectively respond to the sequence and the following data. Further sync information may be sent at regular intervals before and after each data transmission.

    3.
    发明专利
    未知

    公开(公告)号：DE3881681D1

    公开(公告)日：1993-07-15

    申请号：DE3881681

    申请日：1988-03-15

    Applicant: IBM

    Inventor： CARON FRANCOIS ,  CHOLAT-NAMY JEAN ,  MORLEC EMILE

    IPC: H04B1/74 ,  H04L12/00 ,  H04M11/06

    Abstract: The switching circuit provides points (as 18) for connecting permanently the transmitter (12) of a control device (11) to the transmitting side of the telephone switches network, as soon as the control device has been warned of failure of the tributary link. A detecting circuit (31) is connected between the receiving side of the telephone switched network and the receiver (16) of the control device. The circuit is operative for detecting a heading signal sent by the tributary station associated to the tributary link which has failed. A two-position switch (30) is controlled by the control device (11) for disconnecting the receiver (16) from the receiving side of the principal link and for connecting it to the receiving side of the telephone switched network in response to reception by the control device of a heading signal.

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