公开(公告)号：CA2111783A1

公开(公告)日：1994-07-27

申请号：CA2111783

申请日：1993-12-17

Applicant: IBM

Inventor： CROUSE RICHARD S ,  CAZZOLLA JOHN J ,  CHANG LUKE L ,  HURTADO MARCO M ,  NGUYEN KHA D ,  RIVERO JOSE L ,  RUIZ JOSE J ,  SALCEDO LOUIS

IPC: G06F15/173 ,  H04L12/44 ,  H04L12/56 ,  H04Q3/52 ,  H04L5/16

Abstract: A serial simplex switch design is provided which includes I/O ports each of which is configurable specifically for attachment to a data communications subsystem or, alternatively, for cascaded connection to a similarly configured I/O port on another switch. The switch provides a packet routing function including input and output buffers for each of its I/O ports wherein packets of control messages sent by one subsystem are temporarily stored prior to being delivered to the appropriate destination subsystem. When configured to be directly attached to a subsystem, the I/O ports separate control messages from incoming integrated data and control message strings. In a cascade configuration, however, a mechanism is provided wherein data and control messages are separated into two physical paths to eliminate the delays associated with integrated data and control message flow through the cascaded I/O port. Each I/O port is configurable to either of these methods of operation by means of programmable latches associated with the I/O port.