公开(公告)号：EP0681298A3

公开(公告)日：1998-08-05

申请号：EP95303029

申请日：1995-05-03

Applicant: IBM

Inventor： NGUYEN KHA D ,  BASNETT DON E JNR ,  SINGKORNRAT PARIPON ,  WATZEL DONALD J

IPC: A63F13/02 ,  G11C5/00 ,  G11C16/10 ,  G11C16/06 ,  A63F9/22

CPC classification number: A63F13/98 ,  A63F13/02 ,  A63F2300/206 ,  G11C16/102

Abstract: Disclosed is a rewritable cartridge that is compatible with commercially available game systems to produce game cartridges at the point-of-sale location. It provides just-in-time delivery of the desired game. Retailers stock uniquely designed game blanks to meet consumer demand. A programming device loads digital content from computer storage to the rewritable game cartridge in an extremely short period of time. The cartridge employs reprogrammable flash memory (30, 32). The unique flash memory enables programming of the rewritable game cartridge in less than 10 seconds. The flash rewritable cartridge (18) contains identification hardware (38) that allows the programmer to verify it as proprietary to a particular manufacturer or authorized dealer. Only those cartridges that are correctly identified are programmed providing a high level of quality control of the manufacturing process. After a cartridge (18) is verified, the operator has the option to initialize the cartridge and input additional information such as store location and cartridge type into the flash memory. The game content can be erased from the cartridge when it is returned, new game content can be programmed and the cartridge can be reused.

公开(公告)号：CA2111783A1

公开(公告)日：1994-07-27

申请号：CA2111783

申请日：1993-12-17

Applicant: IBM

Inventor： CROUSE RICHARD S ,  CAZZOLLA JOHN J ,  CHANG LUKE L ,  HURTADO MARCO M ,  NGUYEN KHA D ,  RIVERO JOSE L ,  RUIZ JOSE J ,  SALCEDO LOUIS

IPC: G06F15/173 ,  H04L12/44 ,  H04L12/56 ,  H04Q3/52 ,  H04L5/16

Abstract: A serial simplex switch design is provided which includes I/O ports each of which is configurable specifically for attachment to a data communications subsystem or, alternatively, for cascaded connection to a similarly configured I/O port on another switch. The switch provides a packet routing function including input and output buffers for each of its I/O ports wherein packets of control messages sent by one subsystem are temporarily stored prior to being delivered to the appropriate destination subsystem. When configured to be directly attached to a subsystem, the I/O ports separate control messages from incoming integrated data and control message strings. In a cascade configuration, however, a mechanism is provided wherein data and control messages are separated into two physical paths to eliminate the delays associated with integrated data and control message flow through the cascaded I/O port. Each I/O port is configurable to either of these methods of operation by means of programmable latches associated with the I/O port.