公开(公告)号：US3911464A

公开(公告)日：1975-10-07

申请号：US36458473

申请日：1973-05-29

Applicant: IBM

Inventor： CHANG WEN HSING ,  LEE HSING-SAN

IPC: G11C11/35 ,  G11C16/04 ,  H01L27/108 ,  H01L29/792 ,  H01L29/78

CPC classification number: G11C11/35 ,  G11C16/0466 ,  H01L27/108 ,  H01L29/792

Abstract: A nonvolatile random access memory array comprising variable threshold insulated gate field effect transistor devices is described. Each memory element is comprised of a variable threshold field effect gate region located adjacent to a single sensing diffusion which is used to sense change in electrical potential of the sensing diffusion as the effective capacitance of the diffusion is coupled into a depletion region under the gate electrode during a READ cycle. Information is written into the memory by selectively applying a field in excess of a critical magnitude across the variable threshold dielectric to cause the device to assume a high or low threshold state. To read information out of the memory, an inversion region extending from the sensing diffusion under the gate region is used to effectively switch, or reconfigure, the equivalent electrical circuit of the device to alter the capacitive loading presented by the device to the sensing diffusion depending upon whether the device is in a high or low threshold condition. Various gate structures for improving the sensitivity of the memory are disclosed along with a single or multiple pulse sensing scheme which increases sensed voltage and reduces fatigue problems usually associated with conventional variable threshold semiconductor devices.

Abstract translation: 描述了包括可变阈值绝缘栅场效应晶体管器件的非易失性随机存取存储器阵列。 每个存储器元件包括位于与单个感测扩散相邻的可变阈值场效应栅极区域，该单独的感测扩散部分用于检测感测扩散电位的变化，因为扩散的有效电容耦合到栅电极下的耗尽区 在READ循环期间。 通过选择性地在可变阈值电介质上施加超过临界幅度的场以使器件呈现高或低阈值状态，将信息写入存储器。 为了读取存储器中的信息，使用从栅极区域下方的感测扩散延伸的反转区域来有效地切换或重新配置器件的等效电路，以将器件所呈现的电容负载改变为感测扩散依赖 关于设备是处于高或低阈值条件。 公开了用于提高存储器的灵敏度的各种门结构以及增加感测电压并减少通常与常规可变阈值半导体器件相关联的疲劳问题的单个或多个脉冲感测方案。

公开(公告)号：DE2325870A1

公开(公告)日：1974-01-17

申请号：DE2325870

申请日：1973-05-22

Applicant: IBM

Inventor： CHANG WEN HSING

IPC: G11C27/04 ,  G11C19/28 ,  H01L21/339 ,  H01L29/762 ,  H01L29/768 ,  H03K19/08

Abstract: A monolithic charge transfer device wherein logic functions are performed is disclosed. A logical AND gate is provided which utilizes a quantized potential well formed in a surface region of a semi-conducting, or semi-insulating, material by a pattern of control electrodes. Various applications of the AND gate structure provide additional logical functions of Exclusive OR and Exclusive NOR gates.

公开(公告)号：DE3170605D1

公开(公告)日：1985-06-27

申请号：DE3170605

申请日：1981-08-19

Applicant: IBM

Inventor： CHANG WEN HSING ,  GHEEWALA TUSHAR RAMESH ,  HARRIS ERIK PRESTON

IPC: H01L27/18 ,  H01L39/02 ,  H01L39/22 ,  H01L39/08

Abstract: In superconductive circuitry including a superconducting ground plane (18), a magnetic flux trapping moat (24) is provided which surrounds a superconductive device (I). The moat is preferably a cut through the superconducting ground plane which extends along a perimeter surrounding the superconducting device, the moat being continuous except for small regions (26) where there is no cut. The small regions serve as current carrying portions to link the ground plane within the moat to the rest of the ground plane outside of the moat. The moat is a flux pinning center so that magnetic flux does not enter the ground plane region located near the superconducting device.