中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.034 seconds)

    Nonvolatile semiconductor memory
    1.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US3911464A

    公开(公告)日：1975-10-07

    申请号：US36458473

    申请日：1973-05-29

    Applicant: IBM

    Inventor： CHANG WEN HSING ,  LEE HSING-SAN

    IPC: G11C11/35 ,  G11C16/04 ,  H01L27/108 ,  H01L29/792 ,  H01L29/78

    CPC classification number: G11C11/35 ,  G11C16/0466 ,  H01L27/108 ,  H01L29/792

    Abstract: A nonvolatile random access memory array comprising variable threshold insulated gate field effect transistor devices is described. Each memory element is comprised of a variable threshold field effect gate region located adjacent to a single sensing diffusion which is used to sense change in electrical potential of the sensing diffusion as the effective capacitance of the diffusion is coupled into a depletion region under the gate electrode during a READ cycle. Information is written into the memory by selectively applying a field in excess of a critical magnitude across the variable threshold dielectric to cause the device to assume a high or low threshold state. To read information out of the memory, an inversion region extending from the sensing diffusion under the gate region is used to effectively switch, or reconfigure, the equivalent electrical circuit of the device to alter the capacitive loading presented by the device to the sensing diffusion depending upon whether the device is in a high or low threshold condition. Various gate structures for improving the sensitivity of the memory are disclosed along with a single or multiple pulse sensing scheme which increases sensed voltage and reduces fatigue problems usually associated with conventional variable threshold semiconductor devices.

    Abstract translation: 描述了包括可变阈值绝缘栅场效应晶体管器件的非易失性随机存取存储器阵列。 每个存储器元件包括位于与单个感测扩散相邻的可变阈值场效应栅极区域，该单独的感测扩散部分用于检测感测扩散电位的变化，因为扩散的有效电容耦合到栅电极下的耗尽区 在READ循环期间。 通过选择性地在可变阈值电介质上施加超过临界幅度的场以使器件呈现高或低阈值状态，将信息写入存储器。 为了读取存储器中的信息，使用从栅极区域下方的感测扩散延伸的反转区域来有效地切换或重新配置器件的等效电路，以将器件所呈现的电容负载改变为感测扩散依赖 关于设备是处于高或低阈值条件。 公开了用于提高存储器的灵敏度的各种门结构以及增加感测电压并减少通常与常规可变阈值半导体器件相关联的疲劳问题的单个或多个脉冲感测方案。

    2.
    发明专利
    未知

    公开(公告)号：DE3887817D1

    公开(公告)日：1994-03-24

    申请号：DE3887817

    申请日：1988-08-18

    Applicant: IBM

    Inventor： LEE HSING-SAN

    IPC: G11C11/41 ,  G11C7/06 ,  G11C11/419

    Abstract: An improved memory sensing control circuit is provided wherein pulses derived from row or word address changes and from column or bit address changes are used to produce set pulses which are applied at optimum time intervals to a sense amplifier. More particularly, the memory sensing control circuit comprises a sense amplifier having a set device (26), first means (90, 100, 106, 114) for producing a pulse for actuating said set device (26), said means including a first path (94) arranged to pass said pulse to said set device (26) during a given period of time and a second path (92) arranged to pass said pulse to said set device (26) during a shorter period of time than said given period of time, and second means (44, 54, 72, 66, 82) responsive to pulses derived from word and bit address transitions for selecting one of said first and second paths (92, 94).

    7.
    发明专利
    未知

    公开(公告)号：DE3887817T2

    公开(公告)日：1994-08-11

    申请号：DE3887817

    申请日：1988-08-18

    Applicant: IBM

    Inventor： LEE HSING-SAN

    IPC: G11C11/41 ,  G11C7/06 ,  G11C11/419

    Abstract: An improved memory sensing control circuit is provided wherein pulses derived from row or word address changes and from column or bit address changes are used to produce set pulses which are applied at optimum time intervals to a sense amplifier. More particularly, the memory sensing control circuit comprises a sense amplifier having a set device (26), first means (90, 100, 106, 114) for producing a pulse for actuating said set device (26), said means including a first path (94) arranged to pass said pulse to said set device (26) during a given period of time and a second path (92) arranged to pass said pulse to said set device (26) during a shorter period of time than said given period of time, and second means (44, 54, 72, 66, 82) responsive to pulses derived from word and bit address transitions for selecting one of said first and second paths (92, 94).

    MEMORY SENSING SYSTEM
    8.
    发明专利
    MEMORY SENSING SYSTEM 未知

    公开(公告)号：DE3165325D1

    公开(公告)日：1984-09-13

    申请号：DE3165325

    申请日：1981-03-12

    Applicant: IBM

    Inventor： LEE HSING-SAN

    IPC: G11C7/06 ,  G11C11/34 ,  G11C11/35

    Abstract: A sensing technique or system is provided for a merged charge memory having similar storage and dummy cells with the dummy cells being charged with a reference voltage equal to 1/2 of the sum of the voltages representing 1 and 0 binary digits of information in the memory. The sensing technique or system includes an insulating layer disposed on a semiconductor substrate, a memory array having a data word line coupled to a first plurality of spaced apart conductive films formed on the insulating layer defining a plurality of data storage capacitors, sensing means having first and second terminals and a dummy line coupled to a second plurality of spaced apart conductive films formed on the insulating layer defining a plurality of reference voltage capacitors. Charge source means are coupled to the first plurality of conductive films by the word line and to the second plurality of conductive films by the dummy line. The first terminal of the sensing means is coupled to a conductive film of the first plurality of films spaced a predetermined distance from the charge source means and the second terminal of the sensing means is coupled to a given conductive film of the second plurality of films spaced the predetermined distance from the charge source means. The reference voltage is derived from the first and second terminals of the sensing means and applied to the given conductive film.

Patent Agency Ranking