公开(公告)号：CA1238717A

公开(公告)日：1988-06-28

申请号：CA502801

申请日：1986-02-26

Applicant: IBM

Inventor： CHAO HU H ,  LU NICKY C

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  H03K19/096

Abstract: YO984-098 BOOST WORD-LINE CLOCK AND DECODER-DRIVER CIRCUITS IN SEMICONDUCTOR MEMORIES A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters are used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock. A high performance decoder circuit is provided in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial. In order to boost the word-line below O V, a negative substrate bias is provided which avoids the junction forward-biasing-due to voltage undershoot below O V at NMOS source or drain, thus simplifying the design and speeding up the word-line clock pull-down when compared to the word-line boost clock circuit without using the substrate bias.