公开(公告)号：CA1271559A

公开(公告)日：1990-07-10

申请号：CA582215

申请日：1988-11-03

Applicant: IBM

Inventor： CHAPPELL BARBARA A ,  CHAPPELL TERRY I ,  SCHUSTER STANLEY E

IPC: G11C11/413 ,  G11C8/10 ,  G11C11/408 ,  G06F11/10

Abstract: YO987-018 HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT FOR SEMICONDUCTOR MEMORIES A high performance decoder/driver circuit for a semiconductor memory having Al to AN (true) and ?? to ?? (complement) address lines for receiving Al to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices connected to Al to AN-1 or ?? to of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node of the decoder and to AN and ?? lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the ?? line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line and is further responsive to the second selection signal to provide an output signal on a second memory word line.

公开(公告)号：DE69018053T2

公开(公告)日：1995-09-28

申请号：DE69018053

申请日：1990-12-13

Applicant: IBM

Inventor： CHAPPELL BARBARA A ,  CHAPPELL TERRY I ,  SCHUSTER STANLEY E

IPC: H03K3/011 ,  H03K3/356 ,  H03K17/14 ,  H03K19/0185 ,  H03K3/01

Abstract: CMOS ECL drive circuit for providing regulated ECL logic levels. A CMOS logic circuit (11) is connected by parallel N channel and P channel devices (29, 30) to serially connected N and P channel devices (26, 27). The serially connected N and P channel devices (26, 27) are connected across a CMOS power supply (Vdd, Vss) with gate connections connected to the logic circuit (11). The parallel devices (29, 30) provide a regulating feedback current to one of the serially connected P channel and N channel devices (26, 27) during each of first and second ECL logic states. The feedback current effectively controls the bias on the gate connections of the serially connected P and N channel devices (26, 27). The voltage at the junction of the serially connected P and N channel devices (26, 27) is regulated by each of the parallel connected devices (29, 30).

公开(公告)号：DE69018053D1

公开(公告)日：1995-04-27

申请号：DE69018053

申请日：1990-12-13

Applicant: IBM

Inventor： CHAPPELL BARBARA A ,  CHAPPELL TERRY I ,  SCHUSTER STANLEY E

IPC: H03K3/011 ,  H03K3/356 ,  H03K17/14 ,  H03K19/0185 ,  H03K3/01

Abstract: CMOS ECL drive circuit for providing regulated ECL logic levels. A CMOS logic circuit (11) is connected by parallel N channel and P channel devices (29, 30) to serially connected N and P channel devices (26, 27). The serially connected N and P channel devices (26, 27) are connected across a CMOS power supply (Vdd, Vss) with gate connections connected to the logic circuit (11). The parallel devices (29, 30) provide a regulating feedback current to one of the serially connected P channel and N channel devices (26, 27) during each of first and second ECL logic states. The feedback current effectively controls the bias on the gate connections of the serially connected P and N channel devices (26, 27). The voltage at the junction of the serially connected P and N channel devices (26, 27) is regulated by each of the parallel connected devices (29, 30).