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    Multipath encoder-decoder arrangement
    1.
    发明授权
    Multipath encoder-decoder arrangement 失效
    多路编码器解码器布置

    公开(公告)号：US3657699A

    公开(公告)日：1972-04-18

    申请号：US3657699D

    申请日：1970-06-30

    Applicant: IBM

    Inventor： ROCHER EDOUARD Y ,  SCHUSTER STANLEY E

    IPC: G11C19/00 ,  G11C19/18 ,  H04K1/06 ,  H04L9/34 ,  G08C25/00

    CPC classification number: H04K1/06 ,  G11C19/00 ,  G11C19/184 ,  H04L9/0637 ,  H04L9/34 ,  H04L2209/12

    Abstract: A multipath encoder-decoder arrangement which consists of a plurality of storage devices such as memory cells, for example, which can be shifted from one series configuration into at least a second series configuration. The storage devices or at least a portion of them are switched from a first series path to a second series path. In one configuration, the outputs of all the storage devices are switched to the input of a succeeding storage device in a first path to the input of a different storage device in a second series path. In another embodiment, only a portion of the storage devices in one path are switched to form a series arrangement of storage devices in a second path in conjunction with fixed interconnections between certain other of the storage devices. By simply switching between paths, the order of information can be changed, i.e., interleaved, in such a way that errors which occur in bursts when transmitting data are spread out over the entire message with an inter-error space large enough to improve error correction. By providing control means which controls the shifting of data along the series configurations and the switching between configurations, in accordance with a given key, it is possible to scramble transmitted data at various levels of complexity. The complexity at one level, for example, is provided by a feedback loop connected between the input and output of the series configurations which permits data held in the series paths to be changed in both position and polarity. Another level of complexity can be achieved by modifying the key with another key which has been logically combined with previously transmitted encoded data. After transmission, the data is received and unscrambled in a similar encoder-decoder arrangement except that the decoding process is effectively reversed.

    Abstract translation: 一种多路径编码器 - 解码器装置，其由诸如存储器单元的多个存储装置组成，其可以从一个串联配置转移到至少第二个串联配置。 存储设备或其至少一部分从第一串行路径切换到第二串行路径。 在一种配置中，将所有存储设备的输出切换到第二路径中的不同存储设备的输入的第一路径中的后续存储设备的输入。 在另一个实施例中，只有一个路径中的一部分存储设备被切换以形成第二路径中的存储设备的串联布置，结合在某些其他存储设备之间的固定互连。 通过简单地在路径之间切换，信息的顺序可以被改变，即交织，使得在发送数据时在突发中出现的错误在整个消息中分散，具有足够大的错误间隔以改善纠错 。 通过提供控制装置，其控制沿着串联配置的数据移位和配置之间的切换，根据给定的键，可以以各种复杂程度对发送的数据进行加扰。 例如，一个级别的复杂性由连接在串联配置的输入和输出之间的反馈回路提供，其允许保持在串联路径中的数据在位置和极性两者上改变。 可以通过使用与先前发送的编码数据进行逻辑组合的另一个键修改密钥来实现另一个复杂度。 在传输之后，以类似的编码器 - 解码器装置接收和解扰数据，除了解码过程被有效地反转。

    HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT FOR SEMICONDUCTOR
    5.
    发明专利
    HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT FOR SEMICONDUCTOR 未知

    公开(公告)号：CA1271559A

    公开(公告)日：1990-07-10

    申请号：CA582215

    申请日：1988-11-03

    Applicant: IBM

    Inventor： CHAPPELL BARBARA A ,  CHAPPELL TERRY I ,  SCHUSTER STANLEY E

    IPC: G11C11/413 ,  G11C8/10 ,  G11C11/408 ,  G06F11/10

    Abstract: YO987-018 HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT FOR SEMICONDUCTOR MEMORIES A high performance decoder/driver circuit for a semiconductor memory having Al to AN (true) and ?? to ?? (complement) address lines for receiving Al to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices connected to Al to AN-1 or ?? to of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node of the decoder and to AN and ?? lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the ?? line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line and is further responsive to the second selection signal to provide an output signal on a second memory word line.

    COMMUNICATION SYSTEM AND METHOD
    7.
    发明专利
    COMMUNICATION SYSTEM AND METHOD 未知

    公开(公告)号：CA963188A

    公开(公告)日：1975-02-18

    申请号：CA130919

    申请日：1971-12-23

    Applicant: IBM

    Inventor： ROCHER EDOUARD Y ,  SCHUSTER STANLEY E

    IPC: H04J3/24 ,  H04L12/43 ,  H04M9/02

    Abstract: A multi-loop multiplex communication system is disclosed wherein a plurality of remote transmitting terminals are connected via a loop to a system controller and wherein a plurality of remote receivers are connected via a second loop to the same system controller. In operation, all communications between devices associated with the first loop, the second loop and the system controller are carried out via assigned time slots in a system time frame. Under control of the system controller, all communications between devices associated with the first loop and devices associated with the second loop are carried out via non-assigned time slots in the system time frame. When device-to-device communications are being carried out, means are provided at the system controller for connecting the first and second loop in series converting the two loops from their essentially parallel operation when devices associated with either loop interact with the system controller. In one embodiment, a variable time delay is provided at the system controller called a compensation delay which, regardless of the loop lengths, in conjunction with the propagation delay, makes the total delay a constant value. This permits the use of the same assigned time slot by the transmitter and receiver associated with a given device and which are connected to different loops. In another embodiment, the delay arrangement is eliminated by providing a third cable which is in parallel with both loops and which provides a bit, byte and frame synchronization for all devices associated with both loops. In the latter arrangement, however, device-to-device communication is still carried out using nonassigned time slots while device-to-system controller and system controller-to-device communications are still carried out on assigned time slots. A controller switching arrangement is shown along with an example of a typical terminal device and, further, a method for operating the multi-loop multiplex communication system is disclosed.

    HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT
    9.
    发明专利
    HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT 未知

    公开(公告)号：CA1223352A

    公开(公告)日：1987-06-23

    申请号：CA485187

    申请日：1985-06-25

    Applicant: IBM

    Inventor： CHAPPELL BARBARA A ,  RAJEEVAKUMAR THEKKEMADATHIL V ,  SCHUSTER STANLEY E ,  TERMAN LEWIS M

    IPC: H03K19/096 ,  G11C8/10 ,  G11C11/34 ,  G11C11/407 ,  G11C11/413 ,  G06F12/02 ,  G11C7/00

    Abstract: HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT A decoder/driver circuit for a semiconductor memory having A1 to AN (true) and ?? to ?? (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 of ?? to ???? of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the ?? line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output signal on a second memory word line.

    C-2C A/D AND D/A CONVERTER
    10.
    发明专利
    C-2C A/D AND D/A CONVERTER 未知

    公开(公告)号：CA1075819A

    公开(公告)日：1980-04-15

    申请号：CA253587

    申请日：1976-05-28

    Applicant: IBM

    Inventor： COOK PETER W ,  SCHUSTER STANLEY E

    IPC: H03M1/74 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H03M1/00 ,  H03K13/02

    Abstract: A C-2C analog-to-digital and digital-to-analog converter is described, the C-2C designation referring to the arrangement of capacitance in a capacitor ladder network. The capacitors are formed in a monolithic, multilayer structure which includes a substrate, diffusion regions in the substrate, a polysilicon layer and an aluminum layer wherein the capacitances are formed between the aluminum layer and the polysilicon layer and between the polysilicon layer and the diffusion region, and these capacitances have the ratio of 2C to C respectively. The capacitor ladder network formed in the multilayer structure can be trimmed or adjusted electrically after manufacture to obtain the desired tolerances.

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