公开(公告)号：FR2295647A1

公开(公告)日：1976-07-16

申请号：FR7533265

申请日：1975-10-20

Applicant: IBM

Inventor： CHECK GLEN P ,  DIMMICK ROGER F

IPC: G05D3/12 ,  G06K15/16 ,  H03K21/02 ,  H03K21/40 ,  H03K23/00

Abstract: A counter circuit counts all transitions of two or more overlapped out of phase bi-level signals under control of a start signal by combining the input signals via an exclusive OR circuit into a single signal having the transitions of all input signals. The levels of this single signal are applied to a polarity hold circuit and the level present upon the occurrence of an asynchronously occurring start signal is stored therein. The polarity hold circuit provides a pair of gating signals to a logical AND/OR network having an output containing both the positive and negative transitions of the single signal. The detected transitions are fed into a binary counter whose first stage consists of the AND/OR network.