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Patent Agency Ranking
公开(公告)号：FR2295647A1
公开(公告)日：1976-07-16
申请号：FR7533265
申请日：1975-10-20
Applicant: IBM
Inventor： CHECK GLEN P , DIMMICK ROGER F
Abstract: A counter circuit counts all transitions of two or more overlapped out of phase bi-level signals under control of a start signal by combining the input signals via an exclusive OR circuit into a single signal having the transitions of all input signals. The levels of this single signal are applied to a polarity hold circuit and the level present upon the occurrence of an asynchronously occurring start signal is stored therein. The polarity hold circuit provides a pair of gating signals to a logical AND/OR network having an output containing both the positive and negative transitions of the single signal. The detected transitions are fed into a binary counter whose first stage consists of the AND/OR network.
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公开(公告)号：BR9006652A
公开(公告)日：1991-10-01
申请号：BR9006652
申请日：1990-12-28
Applicant: IBM
Inventor： AUG CONRAD J , CASANOVA WAYNE J , CORFITS WILLIAM D , DIMMICK ROGER F , WHEELER STEPHEN E
Abstract: A double-sided backplane assembly (20) is provided for increasing the logic element density in a logic cage or CEC. The backplane assembly is multi-layered with a backplane card (22) centrally located between a stiffener (30) and an EMC shield (36) affixed to each side thereof. Connectors for connecting logic elements to the backplane card are provided on both sides of the backplane card, so that a logic cage having two sub-cages may be provided, the two sub-cages sharing the one backplane assembly.
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公开(公告)号：CA1047607A
公开(公告)日：1979-01-30
申请号：CA237282
申请日：1975-10-08
Applicant: IBM
Inventor： CHECK GLENN P , DIMMICK ROGER F
Abstract: OVERLAPPED SIGNAL TRANSITION COUNTER A counter circuit counts all transitions of two or more overlapped out of phase bi-level signals under control of a start signal by combining the input signals via an exclusive OR circuit into a single signal having the transitions of all input signals. The levels of this single signal are applied to a polarity hold circuit and the level present upon the occurrence of an asynchronously occurring start signal is stored therein. The polarity hold circuit provides a pair of gating signals to a logical AND/OR network having an output containing both the positive and negative transitions of the single signal. The detected transitions are fed into a binary counter whose first stage consists of the AND/OR network.
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公开(公告)号：FR2722014A1
公开(公告)日：1996-01-05
申请号：FR9505304
申请日：1995-04-27
Applicant: IBM
Inventor： DIMMICK ROGER F , FITTERER GARY A , JAJOWKA JEFF A , OTTO WILLIAM F , RASMUSSEN JERRY R , SOBOTTA TERRY L
Abstract: The first extension card (112) has a microprocessor (123) which is connected to memory modules (SIMM) (122) by a high speed local bus (125). This feature permits high speed processing on the card and limits the number of input-output connecting pins to the main system and the second card (114). The second extension card (114) need not be of the same size as the first and the screw and strut (128, 130) used for mounting both first and second cards permits easy replacement on site of the cards and the (SIMM) memory modules. Protective covers (140) are fitted on either side of the cards.
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公开(公告)号：BR9006651A
公开(公告)日：1991-10-01
申请号：BR9006651
申请日：1990-12-28
Applicant: IBM
Inventor： CASANOVA WAYNE J , CORFITS WILLIAM D , DIMMICK ROGER F , THOMPSON GARY A , THORPE JAMES R , WHEELER STEPHEN E
Abstract: A double-sided central electronics complex (CEC) (20) is provided for increasing the logic card density in a logic cage or CEC. Specifically, two logic cages or sub-enclosures (22, 24) are integrated, sharing one backplane card so that logic elements may be plugged into the CEC from both sides. The CEC is formed by unitary sheet metal side plates, top and bottom cast or guides (26, 28) and a single double-sided backplane assembly (38).
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