1.
    发明专利
    未知

    公开(公告)号:DE68917111T2

    公开(公告)日:1995-03-09

    申请号:DE68917111

    申请日:1989-11-30

    Applicant: IBM

    Inventor: CHEN CHIH-LIANG

    Abstract: This BICMOS driver circuit for high density CMOS logic circuits generates a voltage swing comparable to the CMOS logic circuit voltage swing with improved delay and noise immunity characteristics. A pair of complementary bipolar transistors (35, 36) is connected to a CMOS logic network (30). The transistors have serially connected collectors forming an output node (27) and emitters connected to opposite terminals of a bipolar voltage source (Vdd, Vss). Two FET transistors (40, 41) are connected between the base of each bipolar transistor and a CMOS operating voltage source (Vh, Vl). The CMOS logic network will switch one or the other bipolar transistor on while the other bipolar transistor is held off by its connected FET transistor.

    2.
    发明专利
    未知

    公开(公告)号:DE68917111D1

    公开(公告)日:1994-09-01

    申请号:DE68917111

    申请日:1989-11-30

    Applicant: IBM

    Inventor: CHEN CHIH-LIANG

    Abstract: This BICMOS driver circuit for high density CMOS logic circuits generates a voltage swing comparable to the CMOS logic circuit voltage swing with improved delay and noise immunity characteristics. A pair of complementary bipolar transistors (35, 36) is connected to a CMOS logic network (30). The transistors have serially connected collectors forming an output node (27) and emitters connected to opposite terminals of a bipolar voltage source (Vdd, Vss). Two FET transistors (40, 41) are connected between the base of each bipolar transistor and a CMOS operating voltage source (Vh, Vl). The CMOS logic network will switch one or the other bipolar transistor on while the other bipolar transistor is held off by its connected FET transistor.

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